From: Jani Nikula <jani.nikula@linux.intel.com>
To: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com,
chaitanya.kumar.borah@intel.com
Subject: Re: [PATCH 2/2] drm/i915/display: Don't wait for vblank for LUT DSB programming
Date: Thu, 27 Feb 2025 14:40:31 +0200 [thread overview]
Message-ID: <87ldtr36io.fsf@intel.com> (raw)
In-Reply-To: <20250225180905.1588084-3-chaitanya.kumar.borah@intel.com>
On Tue, 25 Feb 2025, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> From PTL, LUT registers are made double buffered. With this change,
> we don't need to wait for vblank to program them. Start DSB1 for
> programming them without waiting for vblank.
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 919e236a9650..9c3fdfcd6759 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7352,6 +7352,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> {
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_display *display = to_intel_display(state);
Please always put display local variable first.
>
> if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank)
> return;
> @@ -7408,7 +7409,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>
> if (new_crtc_state->dsb_color_vblank)
> intel_dsb_chain(state, new_crtc_state->dsb_commit,
> - new_crtc_state->dsb_color_vblank, true);
> + new_crtc_state->dsb_color_vblank,
> + HAS_DOUBLE_BUFFERED_LUT(display) ? false : true);
HAS_DOUBLE_BUFFERED_LUT(display) ? false : true
=>
!HAS_DOUBLE_BUFFERED_LUT(display)
>
> intel_dsb_finish(new_crtc_state->dsb_commit);
> }
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-02-27 12:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-25 18:09 [PATCH 0/2] drm/xe/display: Program double buffered LUT registers Chaitanya Kumar Borah
2025-02-25 18:09 ` [PATCH 1/2] drm/i915/display: Add MMIO path for double-buffered " Chaitanya Kumar Borah
2025-02-28 15:14 ` Ville Syrjälä
2025-03-04 14:43 ` Borah, Chaitanya Kumar
2025-03-04 15:49 ` Ville Syrjälä
2025-04-02 15:39 ` Borah, Chaitanya Kumar
2025-02-25 18:09 ` [PATCH 2/2] drm/i915/display: Don't wait for vblank for LUT DSB programming Chaitanya Kumar Borah
2025-02-27 12:40 ` Jani Nikula [this message]
2025-03-04 14:07 ` Borah, Chaitanya Kumar
2025-02-28 16:31 ` Ville Syrjälä
2025-03-04 14:31 ` Borah, Chaitanya Kumar
2025-03-19 12:18 ` Borah, Chaitanya Kumar
2025-02-27 16:15 ` ✓ CI.Patch_applied: success for drm/xe/display: Program double buffered LUT registers (rev4) Patchwork
2025-02-27 16:16 ` ✓ CI.checkpatch: " Patchwork
2025-02-27 16:17 ` ✓ CI.KUnit: " Patchwork
2025-02-27 16:34 ` ✓ CI.Build: " Patchwork
2025-02-27 16:36 ` ✓ CI.Hooks: " Patchwork
2025-02-27 16:37 ` ✗ CI.checksparse: warning " Patchwork
2025-02-27 16:56 ` ✓ Xe.CI.BAT: success " Patchwork
2025-02-27 17:52 ` ✗ Fi.CI.SPARSE: warning " Patchwork
2025-02-27 18:08 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-27 20:36 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-28 3:42 ` ✗ i915.CI.Full: " Patchwork
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