Re: [PATCH v3 06/22] MIPS: Refactor mips_cps_core_entry implementation

[Gregory CLEMENT <gregory.clement@bootlin.com>]

Hello Jiaxun,

> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> Now the exception vector for CPS systems are allocated on-fly
> with memblock as well.
>
> It will try to allocate from KSEG1 first, and then try to allocate
> in low 4G if possible.
>
> The main reset vector is now generated by uasm, to avoid tons
> of patches to the code. Other vectors are copied to the location
> later.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
[...]


> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
[...]

> +static int __init setup_cps_vecs(void)
> +{
> +	extern void excep_tlbfill(void);
> +	extern void excep_xtlbfill(void);
> +	extern void excep_cache(void);
> +	extern void excep_genex(void);
> +	extern void excep_intex(void);
> +	extern void excep_ejtag(void);
> +	phys_addr_t cps_vec_pa;
> +	void *cps_vec;
> +
> +	/* Try to allocate in KSEG1 first */
> +	cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
> +						0x0, KSEGX_SIZE - 1);
> +
> +	if (cps_vec_pa)
> +		core_entry_reg = CKSEG1ADDR(cps_vec_pa) &
> +					CM_GCR_Cx_RESET_BASE_BEVEXCBASE;
> +
> +	if (!cps_vec_pa && mips_cm_is64) {
> +		cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN,
> +							0x0, SZ_4G - 1);
> +		if (cps_vec_pa)
> +			core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) |
> +					CM_GCR_Cx_RESET_BASE_MODE;
> +	}
> +
> +	if (!cps_vec_pa)
> +		return -ENOMEM;
> +
> +	/* We want to ensure cache is clean before writing uncached mem */
> +	blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE);
> +	bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE);
> +	__sync();
> +
> +	cps_vec = (void *)TO_UNCAC(cps_vec_pa);

Following your remark about the configuration for generic mips32[1]. I made
some changes and tried to build with the following command:
make 32r6el_defconfig; make

I got the follower error:
arch/mips/kernel/smp-cps.c: In function ‘setup_cps_vecs’:
arch/mips/kernel/smp-cps.c:162:19: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]

The issue comes from the TO_UNCAC macro that use the TO_PHYS_MASK macro
which is 64 bits, so it turn the size of TO_UNCAC() to 8 bytes while the
size of a pointer is 4 bytes.

Actually it show that TO_UNCAC was created to be only used for 64 bits,
and it was only your patch "MIPS: spaces: Define a couple of handy
macros" that made possible to use in 32 bit case.

Did you mange to build a kernel in 32 bits configuration ?
Maybe you had a local patch that made it possible.

I propose the following fix to squash into the patch "MIPS: spaces:
Define a couple of handy macros" , what do you think of it?

diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 05db19521e817..4884199d8b8c4 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -49,6 +49,9 @@
 #define HIGHMEM_START          _AC(0x20000000, UL)
 #endif
 
+#define TO_UNCAC(x)            CKSEG1ADDR(x)
+#define TO_CAC(x)              CKSEG0ADDR(x)
+
 #endif /* CONFIG_32BIT */
 
 #ifdef CONFIG_64BIT
@@ -78,12 +81,12 @@
 #define HIGHMEM_START          (_AC(1, UL) << _AC(59, UL))
 #endif
 
+#define TO_UNCAC(x)            (UNCAC_BASE | ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)              (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_PHYS(x)             (             ((x) & TO_PHYS_MASK))
 
 #endif /* CONFIG_64BIT */
 
-#define TO_CAC(x)              (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)            (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 
 /*
  * This handles the memory map.


[1]:https://lore.kernel.org/linux-mips/4eb150cf-3fb7-41c8-accc-06b13e46f086@app.fastmail.com/

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com