Re: [for-4.18] Re: [PATCH v2] ARM: GICv3 ITS: flush caches for newly allocated ITT

[Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>]

Hi Julien, Henry,

Julien Grall <julien@xen.org> writes:

> Hi,
>
> (Adding [for-4.18] in the title for Henry to spot the request)
>
> On 22/09/2023 23:27, Volodymyr Babchuk wrote:
>> ITS manages Device Tables and Interrupt Translation Tables on its own,
>> so generally we are not interested in maintaining any coherence with
>> CPU's view of those memory regions, except one case: ITS requires that
>> Interrupt Translation Tables should be initialized with
>> zeroes. Existing code already does this, but it does not cleans
>> caches afterwards. This means that ITS may see un-initialized ITT and
>> CPU can overwrite portions of ITT later, when it finally decides to
>> flush caches. Visible effect of this issue that there are not
>> interrupts delivered from a device.
>> Fix this by calling clean_and_invalidate_dcache_va_range() for newly
>> allocated ITT.
>> 
>
> I would consider to add:
>
> Fixes: 69082e1c210d ("ARM: GICv3 ITS: introduce device mapping")

May I ask you (or Henry?) to add this when you'll commit this change? Or
should I publish an updated version?

>> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>
> Reviewed-by: Julien Grall <jgrall@amazon.com>
>
> @Henry, this patch should be low-risk. We are cleaning & invalidating
> the cache, so there should be no change for platform not requiring
> cache maintenance. This should hopefully had support for more
> platform. Note that the GICv3 ITS feature is still experimental.
>
> Based on what I wrote above, would you be OK to have this patch in 4.18?


-- 
WBR, Volodymyr