From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 289F5C433EF for ; Mon, 18 Apr 2022 13:31:02 +0000 (UTC) Received: from localhost ([::1]:53936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ngRT2-0000dN-Sn for qemu-devel@archiver.kernel.org; Mon, 18 Apr 2022 09:31:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ngRRQ-0008DP-A6 for qemu-devel@nongnu.org; Mon, 18 Apr 2022 09:29:20 -0400 Received: from mail11.asahi-net.or.jp ([202.224.55.51]:52224) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ngRRO-0003or-Fo for qemu-devel@nongnu.org; Mon, 18 Apr 2022 09:29:19 -0400 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail11.asahi-net.or.jp (Postfix) with ESMTPA id D0731274B0; Mon, 18 Apr 2022 22:29:13 +0900 (JST) Received: from SIOS1075.ysato.ml (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 042AF1C0173; Mon, 18 Apr 2022 22:29:12 +0900 (JST) Date: Mon, 18 Apr 2022 22:29:12 +0900 Message-ID: <87lew2msev.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Tomoaki Kawada Subject: Re: [PATCH] target/rx: swap stack pointers on clrpsw/setpsw instruction In-Reply-To: <20220416032009.1897719-1-i@yvt.jp> References: <20220416032009.1897719-1-i@yvt.jp> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Received-SPF: softfail client-ip=202.224.55.51; envelope-from=ysato@users.sourceforge.jp; helo=mail11.asahi-net.or.jp X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, 16 Apr 2022 12:20:09 +0900, Tomoaki Kawada wrote: > > The control register field PSW.U determines which stack pointer register > (ISP or USP) is mapped as R0. In QEMU, this is implemented by having a > value copied between ISP or USP and R0 whenever PSW.U is updated or > access to ISP/USP is made by an mvtc/mvic instruction. However, this > update process was incorrectly omitted in the clrpsw/setpsw (clear/set > PSW) instructions, causing stack pointers to go out-of-sync. > > This patch updates the clrpsw/setpsw translator to handle PSW.U updates > correctly and fix this problem. > > Signed-off-by: Tomoaki Kawada > --- > target/rx/translate.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/target/rx/translate.c b/target/rx/translate.c > index 5db8f79a82..c282433fb7 100644 > --- a/target/rx/translate.c > +++ b/target/rx/translate.c > @@ -2135,6 +2135,7 @@ enum { > > static inline void clrsetpsw(DisasContext *ctx, int cb, int val) > { > + TCGv z; > if (cb < 8) { > switch (cb) { > case PSW_C: > @@ -2160,7 +2161,22 @@ static inline void clrsetpsw(DisasContext *ctx, int cb, int val) > ctx->base.is_jmp = DISAS_UPDATE; > break; > case PSW_U: > + z = tcg_const_i32(0); > + > + /* (PSW.U ? USP : ISP) = R0 */ > + tcg_gen_movcond_i32(TCG_COND_NE, cpu_usp, > + cpu_psw_u, z, cpu_sp, cpu_usp); > + tcg_gen_movcond_i32(TCG_COND_EQ, cpu_isp, > + cpu_psw_u, z, cpu_sp, cpu_isp); > + > + /* Set PSW.U */ > tcg_gen_movi_i32(cpu_psw_u, val); > + > + /* R0 = (PSW.U ? USP : ISP) */ > + tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp, > + cpu_psw_u, z, cpu_usp, cpu_isp); > + > + tcg_temp_free(z); > break; > default: > qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); > -- > 2.35.1 > Overall looks good. I have same comment as Richard. Can you fix it like his comment? Thaks. -- Yosinori Sato