From: Thomas Gleixner <tglx@linutronix.de>
To: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Cc: Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "Rafael J . Wysocki" <rjw@rjwysocki.net>,
"H . Peter Anvin" <hpa@zytor.com>,
Tony Luck <tony.luck@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Andi Kleen <ak@linux.intel.com>,
Kuppuswamy Sathyanarayanan <knsathya@kernel.org>,
linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH v2] x86: Skip WBINVD instruction for VM guest
Date: Fri, 03 Dec 2021 00:48:43 +0100 [thread overview]
Message-ID: <87lf126010.ffs@tglx> (raw)
In-Reply-To: <20211202222109.pcsgm2jska3obvmx@black.fi.intel.com>
Kirill,
On Fri, Dec 03 2021 at 01:21, Kirill A. Shutemov wrote:
> On Thu, Nov 25, 2021 at 01:40:24AM +0100, Thomas Gleixner wrote:
>> Kuppuswamy,
>> Either that or you provide patches with arguments which are based on
>> proper analysis and not on 'appears to' observations.
>
> I think the right solution to the WBINVD would be to add a #VE handler
> that does nothing. We don't have a reasonable way to handle it from within
> the guest. We can call the VMM in hope that it would handle it, but VMM is
> untrusted and it can ignore the request.
>
> Dave suggested that we need to do code audit to make sure that there's no
> user inside TDX guest environment that relies on WBINVD to work correctly.
>
> Below is full call tree of WBINVD. It is substantially larger than I
> anticipated from initial grep.
>
> Conclusions:
>
> - Most of callers are in ACPI code on changing S-states. Ignoring cache
> flush for S-state change on virtual machine should be safe.
>
> - The only WBINVD I was able to trigger is on poweroff from ACPI code.
> Reboot also should trigger it, but for some reason I don't see it.
>
> - Few caller in CPU offline code. TDX does not allowed to offline CPU as
> we cannot bring it back -- we don't have SIPI. And even if offline
> works for vCPU it should be safe to ignore WBINVD there.
>
> - NVDIMMs are not supported inside TDX. If it will change we would need
> to deal with cache flushing for this case. Hopefully, we would be able
> to avoid WBINVD.
>
> - Cache QoS and MTRR use WBINVD. They are disabled in TDX, but it is
> controlled by VMM if the feature is advertised. We would need to
> filter CPUID/MSRs to make sure VMM would not mess with them.
>
> Is it good enough justification for do-nothing #VE WBINVD handler?
first of all thank you very much for this very profound analysis.
This is really what I was asking for and you probably went even a step
deeper than that. Very appreciated.
What we should do instead of doing a wholesale let's ignore WBINVD is to
have a separate function/macro:
ACPI_FLUSH_CPU_CACHE_PHYS()
and invoke that from the functions which are considered to be safe.
That would default to ACPI_FLUSH_CPU_CACHE() for other architecures
obviously.
Then you can rightfully do:
#define ACPI_FLUSH_CPU_CACHE_PHYS() \
if (!cpu_feature_enabled(XXX)) \
wbinvd(); \
where $XXX might be FEATURE_TDX_GUEST for paranoia sake and then
extended to X86_FEATURE_HYPERVISOR if everyone agrees.
Then you have the #VE handler which just acts on any other wbinvd
invocation via warn, panic, whatever, no?
Thanks,
tglx
next prev parent reply other threads:[~2021-12-02 23:48 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-16 0:50 [PATCH v1 1/1] x86: Skip WBINVD instruction for VM guest Kuppuswamy Sathyanarayanan
2021-11-16 16:24 ` Borislav Petkov
2021-11-16 16:36 ` Sathyanarayanan Kuppuswamy
2021-11-19 4:03 ` [PATCH v2] " Kuppuswamy Sathyanarayanan
2021-11-25 0:40 ` Thomas Gleixner
2021-12-02 22:21 ` Kirill A. Shutemov
2021-12-02 22:38 ` Dave Hansen
2021-12-02 23:48 ` Thomas Gleixner [this message]
2021-12-03 23:49 ` Kirill A. Shutemov
2021-12-04 0:20 ` Dave Hansen
2021-12-04 0:54 ` Kirill A. Shutemov
2021-12-06 15:35 ` Dave Hansen
2021-12-06 16:39 ` Dan Williams
2021-12-06 16:53 ` Dave Hansen
2021-12-06 17:51 ` Dan Williams
2021-12-04 20:27 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 0/4] ACPI/ACPICA: Only flush caches on S1/S2/S3 and C3 Kirill A. Shutemov
2021-12-06 12:29 ` [PATCH 1/4] ACPICA: Do not flush cache for on entering S4 and S5 Kirill A. Shutemov
2021-12-08 14:58 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 2/4] ACPI: PM: Remove redundant cache flushing Kirill A. Shutemov
2021-12-07 16:35 ` Rafael J. Wysocki
2021-12-09 13:32 ` Kirill A. Shutemov
2021-12-17 18:04 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 3/4] ACPI: processor idle: Only flush cache on entering C3 Kirill A. Shutemov
2021-12-06 15:03 ` Peter Zijlstra
2021-12-08 16:26 ` Rafael J. Wysocki
2021-12-09 13:33 ` Kirill A. Shutemov
2021-12-17 17:58 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 4/4] ACPI: PM: Avoid cache flush on entering S4 Kirill A. Shutemov
2021-12-08 15:10 ` Rafael J. Wysocki
2021-12-08 16:04 ` Kirill A. Shutemov
2021-12-08 16:16 ` Rafael J. Wysocki
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