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Tue, 12 Oct 2021 07:59:35 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 211711FF96; Tue, 12 Oct 2021 15:59:35 +0100 (BST) References: <20211012093128.3909859-1-alex.bennee@linaro.org> User-agent: mu4e 1.7.0; emacs 28.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Subject: Re: [RFC PATCH] target/s390x: don't double ld_code() when reading instructions Date: Tue, 12 Oct 2021 15:52:13 +0100 In-reply-to: Message-ID: <87lf2ywap4.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:S390 TCG CPUs" , Thomas Huth , Cornelia Huck , qemu-devel@nongnu.org, David Hildenbrand Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 10/12/21 2:31 AM, Alex Benn=C3=A9e wrote: >> For the 4 byte instruction case we started doing an ld_code2 and then >> reloaded the data with ld_code4 once it was identified as a 4 byte op. >> This is confusing for the plugin hooks which are expecting to see >> simple sequential loading so end up reporting a malformed 6 byte >> instruction buffer. > > I think the plugin stuff could be more clever, knowing where the read > occurs within the sequence. Otherwise, we should simplify the > interface so that it is not possible to make this mistake. It's plugin_insn_append which is doing the tracking here so we could extend the interface to include the current pc of the load and make the appropriate adjustments. That said it's a bunch hoops to jump every instruction when we could just as easily add an assert and fix up any cases where we do. I guess it comes down to how prevalent double dipping in the instruction stream is when constructing a translation? What happens if the protection of the code area changes half way through a translation? Could a mapping change in flight? > > > r~ --=20 Alex Benn=C3=A9e