From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7574C4338F for ; Wed, 11 Aug 2021 14:47:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7BBD860E93 for ; Wed, 11 Aug 2021 14:47:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7BBD860E93 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uzCztuMPZuKzgo9x0vENzPQaNNFbLjNYivJBH+xsX6Q=; b=AqYkIK0ECDoX7O k+kOvk9o6Updvb5rIlhJ/G5vFeO06PDqUASozOLDfeU48JQ6De0Ct/U3PrtSo/kJVmbZ8ZOVOI0fl CnPaEsOOtPMOqUAYFYrKgH2L1fHzqyt0cSGVzJ20tT/p5Es+dILt/MFnF4eD6/BlU0scemu0ZuZKl 1pUjI93uJVHbbdNQ/acvKkvPx4s1RLcfgGfGkyN9ZqFwUqJEz29F0DCXJ8spQMNkdl0/sCXQ882VB 3P4/5K8ZDUNU37P90d8/UB3U2XSDY0/n4IQ3oongcP7VpBvDEYTpDdPZEKEBlZZQjbqPmDuhFXmnK dJGYqXZEyE0F8XGC3v0g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mDpU6-007T6x-7h; Wed, 11 Aug 2021 14:45:34 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mDpTv-007T5p-R6 for linux-arm-kernel@lists.infradead.org; Wed, 11 Aug 2021 14:45:27 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8981260F21; Wed, 11 Aug 2021 14:45:23 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mDpTt-004MGB-Hv; Wed, 11 Aug 2021 15:45:21 +0100 Date: Wed, 11 Aug 2021 15:45:21 +0100 Message-ID: <87lf589h1a.wl-maz@kernel.org> From: Marc Zyngier To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Oliver Upton Subject: Re: [PATCH][boot-wrapper] aarch64: Enable ECV to allow access to CNTPOFF_EL2 In-Reply-To: <20210811135558.GB72303@C02TD0UTHF1T.local> References: <20210811092226.2316583-1-maz@kernel.org> <20210811135558.GB72303@C02TD0UTHF1T.local> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, oupton@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210811_074523_974348_904F6CE8 X-CRM114-Status: GOOD ( 37.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 11 Aug 2021 14:55:58 +0100, Mark Rutland wrote: > > On Wed, Aug 11, 2021 at 10:22:26AM +0100, Marc Zyngier wrote: > > If the implemnentation supports ID_AA64MMFR0_EL1.ECV==2, > > set SCR_EL3.ECVEn to allow EL2 access to CNTPOFF_EL2. > > I was about to ask if that was a typo (why is this in an MMFR?), but > that is what the ARM ARM says! I was just as surprised. PFR would have made a lot more sense, but I guess someone wanted to use these last four bits as quickly as possible... ;-) > > > Signed-off-by: Marc Zyngier > > --- > > arch/aarch64/boot.S | 11 +++++++++-- > > 1 file changed, 9 insertions(+), 2 deletions(-) > > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > > index 7f208b5..f0aa3cb 100644 > > --- a/arch/aarch64/boot.S > > +++ b/arch/aarch64/boot.S > > @@ -54,10 +54,17 @@ ASM_FUNC(_start) > > 1: > > /* Enable FGT if present */ > > mrs x1, id_aa64mmfr0_el1 > > - ubfx x1, x1, #56, #4 > > - cbz x1, 1f > > + ubfx x2, x1, #56, #4 > > + cbz x2, 1f > > > > orr x0, x0, #(1 << 27) // FGT enable > > +1: > > + /* Enable ECV2 if present (allows CNTPOFF_EL2) */ > > + ubfx x2, x1, #60, #4 > > + cmp x2, #2 > > + bne 1f > > We need to check ID_AA64MMFR0_EL1.ECV >= 2 (to handle any futrue > variants) so the conditional branch needs to be something like `b.lt`. Good point. I'm surprised ECV3 hasn't hit yet! :D > > + > > + orr x0, x0, #(1 << 28) // ECV enable > > Aside from the above, this looks good to me, and I plan to apply this > with the below tweaks (updated patch below): > > * Use b.lt, as above > > * To keep each check self-contained, the ECV check will read > id_aa64mmfr0_el1 itself. That removes the need to keep x1 around, and > so we can leave the FGT check as-is. > > As part of some cleanup, I'm planning to move this to C, where feature > checks will read ID fields via a helepr that implicitly reads the > register, like: > > if (read_reg_field(ID_AA64MMFR0_EL1, ECV) >= 2) > scr |= SCR_EL3_ECVEN; If you are actively rewriting this, maybe don't bother with the patch and just add this as part of your rewrite. > > Thanks, > Mark. > ---->8---- > From bc6a9380eb3c5afc96735a54d455f2487df48700 Mon Sep 17 00:00:00 2001 > From: Marc Zyngier > Date: Wed, 11 Aug 2021 10:22:26 +0100 > Subject: [PATCH] aarch64: Enable ECV to allow access to CNTPOFF_EL2 > > If the implemnentation supports ID_AA64MMFR0_EL1.ECV==2, > set SCR_EL3.ECVEn to allow EL2 access to CNTPOFF_EL2. > > Signed-off-by: Marc Zyngier > [Mark: read id_aa64mmfr0_el1 separately, s/bne/b.lt/] > Signed-off-by: Mark Rutland > --- > arch/aarch64/boot.S | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 7f208b5..2215f7e 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -59,6 +59,14 @@ ASM_FUNC(_start) > > orr x0, x0, #(1 << 27) // FGT enable > 1: > + /* Enable ECV2 if present (allows CNTPOFF_EL2) */ > + mrs x1, id_aa64mmfr0_el1 > + ubfx x1, x1, #60, #4 > + cmp x1, #2 > + b.lt 1f > + > + orr x0, x0, #(1 << 28) // ECV enable > +1: > /* Enable MTE if present */ > mrs x10, id_aa64pfr1_el1 > ubfx x10, x10, #8, #4 Otherwise looks fine to me. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel