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[91.219.240.2]) by smtp.gmail.com with ESMTPSA id 65sm43820717wre.6.2020.07.21.03.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2020 03:51:43 -0700 (PDT) From: Vitaly Kuznetsov To: Wanpeng Li , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: Paolo Bonzini , Sean Christopherson , Wanpeng Li , Jim Mattson , Joerg Roedel Subject: Re: [PATCH 2/2] KVM: LAPIC: Set the TDCR settable bits In-Reply-To: <1595323468-4380-2-git-send-email-wanpengli@tencent.com> References: <1595323468-4380-1-git-send-email-wanpengli@tencent.com> <1595323468-4380-2-git-send-email-wanpengli@tencent.com> Date: Tue, 21 Jul 2020 12:51:42 +0200 Message-ID: <87lfjdp2dd.fsf@vitty.brq.redhat.com> MIME-Version: 1.0 Content-Type: text/plain Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Wanpeng Li writes: > From: Wanpeng Li > > Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR. > Let's record the settable value in the virtual apic page. > > Signed-off-by: Wanpeng Li > --- > arch/x86/kvm/lapic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 4ce2ddd..8f7a14d 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) > case APIC_TDCR: { > uint32_t old_divisor = apic->divide_count; > > - kvm_lapic_set_reg(apic, APIC_TDCR, val); > + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); > update_divide_count(apic); > if (apic->divide_count != old_divisor && > apic->lapic_timer.period) { AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on bare hardware, # wrmsr 0x83e 0xb # rdmsr 0x83e b # wrmsr 0x83e 0xc wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c # rdmsr 0x83e b Shouldn't we fail the write in case (val & ~0xb) ? -- Vitaly