From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/gen12: Invalidate aux table entries forcibly
Date: Wed, 06 May 2020 18:20:22 +0300 [thread overview]
Message-ID: <87lfm5nl8p.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <158877715660.927.5979318415732712309@build.alporthouse.com>
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2020-05-06 15:47:34)
>> Aux table invalidation can fail on update. So
>> next access may cause memory access to be into stale entry.
>>
>> Proposed workaround is to invalidate entries between
>> all batchbuffers.
>
> This sounds like it should have a sunset clause. Do we anticipate being
> able to drop this w/a in future?
Rafael kindly pointed out that Mesa already does this:
https://gitlab.freedesktop.org/mesa/mesa/-/blob/master/src/gallium/drivers/iris/iris_state.c#L5131
So I would say we can drop this patch.
But it makes me wonder that is that LRI dropped for not being whitelisted.
-Mika
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next prev parent reply other threads:[~2020-05-06 15:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 14:47 [Intel-gfx] [PATCH 1/4] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" Mika Kuoppala
2020-05-06 14:47 ` [Intel-gfx] [PATCH 2/4] drm/i915/gen12: Fix HDC pipeline flush Mika Kuoppala
2020-05-06 14:47 ` [Intel-gfx] [PATCH 3/4] drm/i915/gen12: Flush L3 Mika Kuoppala
2020-05-06 17:24 ` Chris Wilson
2020-05-06 14:47 ` [Intel-gfx] [PATCH 4/4] drm/i915/gen12: Invalidate aux table entries forcibly Mika Kuoppala
2020-05-06 14:59 ` Chris Wilson
2020-05-06 15:20 ` Mika Kuoppala [this message]
2020-05-06 15:32 ` Chris Wilson
2020-05-07 22:28 ` Rafael Antognolli
2020-05-06 15:58 ` Mika Kuoppala
2020-05-06 16:44 ` Chris Wilson
2020-05-06 16:53 ` Mika Kuoppala
2020-05-07 2:44 ` Liu, Chuansheng
2020-05-07 6:43 ` Chris Wilson
2020-05-06 19:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" (rev3) Patchwork
2020-05-06 23:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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