From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Date: Thu, 15 Aug 2019 09:08:53 +0000 Subject: Re: [PATCH] drm/i915/tgl: Fix TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT() macro Message-Id: <87lfvug5i2.fsf@intel.com> List-Id: References: <20190815083336.GE27238@mwanda> In-Reply-To: <20190815083336.GE27238@mwanda> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Dan Carpenter , =?utf-8?Q?Jos=C3=A9?= Roberto de Souza Cc: David Airlie , intel-gfx@lists.freedesktop.org, kernel-janitors@vger.kernel.org, dri-devel@lists.freedesktop.org On Thu, 15 Aug 2019, Dan Carpenter wrote: > This macro doesn't work because the right shift has higher precedence > than bitwise AND. > > Fixes: 9749a5b6c09f ("drm/i915/tgl: Fix the read of the DDI that transcoder is attached to") > Signed-off-by: Dan Carpenter Thanks, already fixed by 1cdd8705c7ac ("drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT"). BR, Jani. > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4a947bd0a294..def6dbdc7e2e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9433,7 +9433,7 @@ enum skl_power_gate { > #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) > #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) > #define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT) > -#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TGL_TRANS_DDI_PORT_MASK >> TGL_TRANS_DDI_PORT_SHIFT) - 1) > +#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1) > #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) > #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) > #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) -- Jani Nikula, Intel Open Source Graphics Center From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915/tgl: Fix TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT() macro Date: Thu, 15 Aug 2019 12:08:53 +0300 Message-ID: <87lfvug5i2.fsf@intel.com> References: <20190815083336.GE27238@mwanda> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190815083336.GE27238@mwanda> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Dan Carpenter , =?utf-8?Q?Jos=C3=A9?= Roberto de Souza Cc: David Airlie , intel-gfx@lists.freedesktop.org, kernel-janitors@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCAxNSBBdWcgMjAxOSwgRGFuIENhcnBlbnRlciA8ZGFuLmNhcnBlbnRlckBvcmFjbGUu Y29tPiB3cm90ZToKPiBUaGlzIG1hY3JvIGRvZXNuJ3Qgd29yayBiZWNhdXNlIHRoZSByaWdodCBz aGlmdCBoYXMgaGlnaGVyIHByZWNlZGVuY2UKPiB0aGFuIGJpdHdpc2UgQU5ELgo+Cj4gRml4ZXM6 IDk3NDlhNWI2YzA5ZiAoImRybS9pOTE1L3RnbDogRml4IHRoZSByZWFkIG9mIHRoZSBEREkgdGhh dCB0cmFuc2NvZGVyIGlzIGF0dGFjaGVkIHRvIikKPiBTaWduZWQtb2ZmLWJ5OiBEYW4gQ2FycGVu dGVyIDxkYW4uY2FycGVudGVyQG9yYWNsZS5jb20+CgpUaGFua3MsIGFscmVhZHkgZml4ZWQgYnkg MWNkZDg3MDVjN2FjICgiZHJtL2k5MTUvdGdsOiBGaXggbWlzc2luZwpwYXJlbnRoZXNlcyBvbiBU R0xfVFJBTlNfRERJX0ZVTkNfQ1RMX1ZBTF9UT19QT1JUIikuCgpCUiwKSmFuaS4KCj4gLS0tCj4g IGRyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmggfCAyICstCj4gIDEgZmlsZSBjaGFuZ2Vk LCAxIGluc2VydGlvbigrKSwgMSBkZWxldGlvbigtKQo+Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMv Z3B1L2RybS9pOTE1L2k5MTVfcmVnLmggYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5o Cj4gaW5kZXggNGE5NDdiZDBhMjk0Li5kZWY2ZGJkYzdlMmUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaAo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5 MTVfcmVnLmgKPiBAQCAtOTQzMyw3ICs5NDMzLDcgQEAgZW51bSBza2xfcG93ZXJfZ2F0ZSB7Cj4g ICNkZWZpbmUgIFRSQU5TX0RESV9TRUxFQ1RfUE9SVCh4KQkoKHgpIDw8IFRSQU5TX0RESV9QT1JU X1NISUZUKQo+ICAjZGVmaW5lICBUR0xfVFJBTlNfRERJX1NFTEVDVF9QT1JUKHgpCSgoKHgpICsg MSkgPDwgVEdMX1RSQU5TX0RESV9QT1JUX1NISUZUKQo+ICAjZGVmaW5lICBUUkFOU19ERElfRlVO Q19DVExfVkFMX1RPX1BPUlQodmFsKQkgKCgodmFsKSAmIFRSQU5TX0RESV9QT1JUX01BU0spID4+ IFRSQU5TX0RESV9QT1JUX1NISUZUKQo+IC0jZGVmaW5lICBUR0xfVFJBTlNfRERJX0ZVTkNfQ1RM X1ZBTF9UT19QT1JUKHZhbCkgKCgodmFsKSAmIFRHTF9UUkFOU19ERElfUE9SVF9NQVNLID4+IFRH TF9UUkFOU19ERElfUE9SVF9TSElGVCkgLSAxKQo+ICsjZGVmaW5lICBUR0xfVFJBTlNfRERJX0ZV TkNfQ1RMX1ZBTF9UT19QT1JUKHZhbCkgKCgoKHZhbCkgJiBUR0xfVFJBTlNfRERJX1BPUlRfTUFT SykgPj4gVEdMX1RSQU5TX0RESV9QT1JUX1NISUZUKSAtIDEpCj4gICNkZWZpbmUgIFRSQU5TX0RE SV9NT0RFX1NFTEVDVF9NQVNLCSg3IDw8IDI0KQo+ICAjZGVmaW5lICBUUkFOU19ERElfTU9ERV9T RUxFQ1RfSERNSQkoMCA8PCAyNCkKPiAgI2RlZmluZSAgVFJBTlNfRERJX01PREVfU0VMRUNUX0RW SQkoMSA8PCAyNCkKCi0tIApKYW5pIE5pa3VsYSwgSW50ZWwgT3BlbiBTb3VyY2UgR3JhcGhpY3Mg Q2VudGVyCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCklu dGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRw czovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeA==