From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [RFC PATCH v2 15/23] KVM: arm64/sve: Add SVE support to register access ioctl interface Date: Wed, 21 Nov 2018 15:20:15 +0000 Message-ID: <87lg5mihjk.fsf@linaro.org> References: <1538141967-15375-1-git-send-email-Dave.Martin@arm.com> <1538141967-15375-16-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 6E9B84A30B for ; Wed, 21 Nov 2018 10:20:19 -0500 (EST) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t1ABLl+kohOI for ; Wed, 21 Nov 2018 10:20:18 -0500 (EST) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 0FD3B4A1F2 for ; Wed, 21 Nov 2018 10:20:18 -0500 (EST) Received: by mail-wr1-f65.google.com with SMTP id v6so6081407wrr.12 for ; Wed, 21 Nov 2018 07:20:17 -0800 (PST) In-reply-to: <1538141967-15375-16-git-send-email-Dave.Martin@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Dave Martin Cc: Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org List-Id: kvmarm@lists.cs.columbia.edu CkRhdmUgTWFydGluIDxEYXZlLk1hcnRpbkBhcm0uY29tPiB3cml0ZXM6Cgo+IFRoaXMgcGF0Y2gg YWRkcyB0aGUgZm9sbG93aW5nIHJlZ2lzdGVycyBmb3IgYWNjZXNzIHZpYSB0aGUKPiBLVk1fe0dF VCxTRVR9X09ORV9SRUcgaW50ZXJmYWNlOgo+Cj4gICogS1ZNX1JFR19BUk02NF9TVkVfWlJFRyhu LCBpKSAobiA9IDAuLjMxKSAoaW4gMjA0OC1iaXQgc2xpY2VzKQo+ICAqIEtWTV9SRUdfQVJNNjRf U1ZFX1BSRUcobiwgaSkgKG4gPSAwLi4xNSkgKGluIDI1Ni1iaXQgc2xpY2VzKQo+ICAqIEtWTV9S RUdfQVJNNjRfU1ZFX0ZGUihpKSAoaW4gMjU2LWJpdCBzbGljZXMpCj4KPiBJbiBvcmRlciB0byBh ZGFwdCBncmFjZWZ1bGx5IHRvIGZ1dHVyZSBhcmNoaXRlY3R1cmFsIGV4dGVuc2lvbnMsCj4gdGhl IHJlZ2lzdGVycyBhcmUgZGl2aWRlZCB1cCBpbnRvIHNsaWNlcyBhcyBub3RlZCBhYm92ZTogIHRo ZSBpCj4gcGFyYW1ldGVyIGRlbm90ZXMgdGhlIHNsaWNlIGluZGV4Lgo+Cj4gRm9yIHNpbXBsaWNp dHksIGJpdHMgb3Igc2xpY2VzIHRoYXQgZXhjZWVkIHRoZSBtYXhpbXVtIHZlY3Rvcgo+IGxlbmd0 aCBzdXBwb3J0ZWQgZm9yIHRoZSB2Y3B1IGFyZSBpZ25vcmVkIGZvciBLVk1fU0VUX09ORV9SRUcs IGFuZAo+IHJlYWQgYXMgemVybyBmb3IgS1ZNX0dFVF9PTkVfUkVHLgo+Cj4gRm9yIHRoZSBjdXJy ZW50IGFyY2hpdGVjdHVyZSwgb25seSBzbGljZSBpID0gMCBpcyBzaWduaWZpY2FudC4gIFRoZQo+ IGludGVyZmFjZSBkZXNpZ24gYWxsb3dzIGkgdG8gaW5jcmVhc2UgdG8gdXAgdG8gMzEgaW4gdGhl IGZ1dHVyZSBpZgo+IHJlcXVpcmVkIGJ5IGZ1dHVyZSBhcmNoaXRlY3R1cmFsIGFtZW5kbWVudHMu Cj4KPiBUaGUgcmVnaXN0ZXJzIGFyZSBvbmx5IHZpc2libGUgZm9yIHZjcHVzIHRoYXQgaGF2ZSBT VkUgZW5hYmxlZC4KPiBUaGV5IGFyZSBub3QgZW51bWVyYXRlZCBieSBLVk1fR0VUX1JFR19MSVNU IG9uIHZjcHVzIHRoYXQgZG8gbm90Cj4gaGF2ZSBTVkUuICBJbiBhbGwgY2FzZXMsIHN1cnBsdXMg c2xpY2VzIGFyZSBub3QgZW51bWVyYXRlZCBieQo+IEtWTV9HRVRfUkVHX0xJU1QuCj4KPiBBY2Nl c3NlcyB0byB0aGUgRlBTSU1EIHJlZ2lzdGVycyB2aWEgS1ZNX1JFR19BUk1fQ09SRSBpcyBub3QK PiBhbGxvd2VkIGZvciBTVkUtZW5hYmxlZCB2Y3B1czogU1ZFLWF3YXJlIHVzZXJzcGFjZSBjYW4g dXNlIHRoZQo+IEtWTV9SRUdfQVJNNjRfU1ZFX1pSRUcoKSBpbnRlcmZhY2UgaW5zdGVhZCB0byBh Y2Nlc3MgdGhlIHNhbWUKPiByZWdpc3RlciBzdGF0ZS4gIFRoaXMgYXZvaWRzIHNvbWUgY29tcGxl eCBhbmQgcG9pbnRsZXNzIGVtbHVhdGlvbgo+IGluIHRoZSBrZXJuZWwuCj4KPiBTaWduZWQtb2Zm LWJ5OiBEYXZlIE1hcnRpbiA8RGF2ZS5NYXJ0aW5AYXJtLmNvbT4KPiAtLS0KPgo+IENoYW5nZXMg c2luY2UgUkZDdjE6Cj4KPiAgKiBSZWZhY3RvcmVkIHRvIHJlbW92ZSBlbXVsYXRpb24gb2YgRlBT SU1EIHJlZ2lzdGVycyB3aXRoIHRoZSBTVkUKPiAgICByZWdpc3RlciB2aWV3IGFuZCB2aWNlLXZl cnNhLiAgVGhpcyBzaW1wbGlmaWVzIHRoZSBjb2RlIGEgZmFpciBiaXQuCj4KPiAgKiBGaXhlZCBh IGNvdXBsZSBvZiByYW5nZSBlcnJvcnMuCj4KPiAgKiBJbmxpbmVkIHZhcmlvdXMgdHJpdmlhbCBo ZWxwZXJzIHRoYXQgbm93IGhhdmUgb25seSBvbmUgY2FsbCBzaXRlLgo+Cj4gICogVXNlIEtWTV9S RUdfU0laRSgpIGFzIGEgc3ltYm9saWMgd2F5IG9mIGdldHRpbmcgU1ZFIHJlZ2lzdGVyIHNsaWNl Cj4gICAgc2l6ZXMuCj4gLS0tCj4gIGFyY2gvYXJtNjQvaW5jbHVkZS91YXBpL2FzbS9rdm0uaCB8 ICAxMCArKysKPiAgYXJjaC9hcm02NC9rdm0vZ3Vlc3QuYyAgICAgICAgICAgIHwgMTQ3ICsrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKystLS0tCj4gIDIgZmlsZXMgY2hhbmdlZCwgMTQ1 IGluc2VydGlvbnMoKyksIDEyIGRlbGV0aW9ucygtKQo+Cj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJt NjQvaW5jbHVkZS91YXBpL2FzbS9rdm0uaCBiL2FyY2gvYXJtNjQvaW5jbHVkZS91YXBpL2FzbS9r dm0uaAo+IGluZGV4IDk3YzM0NzguLjFmZjY4ZmEgMTAwNjQ0Cj4gLS0tIGEvYXJjaC9hcm02NC9p bmNsdWRlL3VhcGkvYXNtL2t2bS5oCj4gKysrIGIvYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNt L2t2bS5oCj4gQEAgLTIyNiw2ICsyMjYsMTYgQEAgc3RydWN0IGt2bV92Y3B1X2V2ZW50cyB7Cj4g IAkJCQkJIEtWTV9SRUdfQVJNX0ZXIHwgKChyKSAmIDB4ZmZmZikpCj4gICNkZWZpbmUgS1ZNX1JF R19BUk1fUFNDSV9WRVJTSU9OCUtWTV9SRUdfQVJNX0ZXX1JFRygwKQo+Cj4gKy8qIFNWRSByZWdp c3RlcnMgKi8KPiArI2RlZmluZSBLVk1fUkVHX0FSTTY0X1NWRQkJKDB4MTUgPDwgS1ZNX1JFR19B Uk1fQ09QUk9DX1NISUZUKQo+ICsjZGVmaW5lIEtWTV9SRUdfQVJNNjRfU1ZFX1pSRUcobiwgaSkJ KEtWTV9SRUdfQVJNNjQgfCBLVk1fUkVHX0FSTTY0X1NWRSB8IFwKPiArCQkJCQkgS1ZNX1JFR19T SVpFX1UyMDQ4IHwJCVwKPiArCQkJCQkgKChuKSA8PCA1KSB8IChpKSkKPiArI2RlZmluZSBLVk1f UkVHX0FSTTY0X1NWRV9QUkVHKG4sIGkpCShLVk1fUkVHX0FSTTY0IHwgS1ZNX1JFR19BUk02NF9T VkUgfCBcCj4gKwkJCQkJIEtWTV9SRUdfU0laRV9VMjU2IHwJCVwKPiArCQkJCQkgKChuKSA8PCA1 KSB8IChpKSB8IDB4NDAwKQoKV2hhdCdzIHRoZSAweDQwMCBmb3I/IEFyZW4ndCBQUkVHJ3MgYWxy ZWFkeSB1bmlxdWUgYnkgYmVpbmcgMjU2IGJpdCB2cwp0aGUgWiByZWdzIDIwNDggYml0IHNpemU/ Cgo+ICsjZGVmaW5lIEtWTV9SRUdfQVJNNjRfU1ZFX0ZGUihpKQlLVk1fUkVHX0FSTTY0X1NWRV9Q UkVHKDE2LCBpKQo+ICsKPiAgLyogRGV2aWNlIENvbnRyb2wgQVBJOiBBUk0gVkdJQyAqLwo+ICAj ZGVmaW5lIEtWTV9ERVZfQVJNX1ZHSUNfR1JQX0FERFIJMAo+ICAjZGVmaW5lIEtWTV9ERVZfQVJN X1ZHSUNfR1JQX0RJU1RfUkVHUwkxCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQva3ZtL2d1ZXN0 LmMgYi9hcmNoL2FybTY0L2t2bS9ndWVzdC5jCj4gaW5kZXggOTUzYTVjOS4uMzIwZGIwZiAxMDA2 NDQKPHNuaXA+Cj4KPiBAQCAtMTMwLDYgKzE1NCwxMDcgQEAgc3RhdGljIGludCBzZXRfY29yZV9y ZWcoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCBjb25zdCBzdHJ1Y3Qga3ZtX29uZV9yZWcgKnJlZykK PiAgCXJldHVybiBlcnI7Cj4gIH0KPgo+ICtzdHJ1Y3Qga3JlZ19yZWdpb24gewo+ICsJY2hhciAq a3B0cjsKPiArCXNpemVfdCBzaXplOwo+ICsJc2l6ZV90IHplcm9wYWQ7Cj4gK307Cj4gKwo+ICsj ZGVmaW5lIFNWRV9SRUdfU0xJQ0VfU0hJRlQJMAo+ICsjZGVmaW5lIFNWRV9SRUdfU0xJQ0VfQklU Uwk1Cj4gKyNkZWZpbmUgU1ZFX1JFR19JRF9TSElGVAkoU1ZFX1JFR19TTElDRV9TSElGVCArIFNW RV9SRUdfU0xJQ0VfQklUUykKPiArI2RlZmluZSBTVkVfUkVHX0lEX0JJVFMJCTUKPiArCj4gKyNk ZWZpbmUgU1ZFX1JFR19TTElDRV9NQVNLIFwKPiArCShHRU5NQVNLKFNWRV9SRUdfU0xJQ0VfQklU UyAtIDEsIDApIDw8IFNWRV9SRUdfU0xJQ0VfU0hJRlQpCj4gKyNkZWZpbmUgU1ZFX1JFR19JRF9N QVNLCVwKPiArCShHRU5NQVNLKFNWRV9SRUdfSURfQklUUyAtIDEsIDApIDw8IFNWRV9SRUdfSURf U0hJRlQpCj4gKwoKSSBndWVzcyB0aGlzIGFsbCBjb21lcyBvdXQgaW4gdGhlIHdhc2ggb25jZSB0 aGUgY29uc3RhbnRzIGFyZSBmb2xkZWQgYnV0CkdFTk1BU0sgZG9lcyBzZWVtIHRvIGJlIGRlc2ln bmVkIGZvciBhcmJpdHJhcnkgYml0IHBvc2l0aW9uczoKCiAgI2RlZmluZSBTVkVfUkVHX1NMSUNF X01BU0sgXAogICAgIEdFTl9NQVNLKFNWRV9SRUdfU0xJQ0VfQklUUyArIFNWRV9SRUdfU0xJQ0Vf U0hJRlQgLSAxLCBTVkVfUkVHX1NMSUNFX1NISUZUKQoKSG1tIEkgZ3Vlc3MgdGhhdCBtaWdodCBi ZSBldmVuIGhhcmRlciB0byBmb2xsb3cuLi4KCj4gKyNkZWZpbmUgU1ZFX05VTV9TTElDRVMgKDEg PDwgU1ZFX1JFR19TTElDRV9CSVRTKQo+ICsKPiArc3RhdGljIGludCBzdmVfcmVnX3JlZ2lvbihz dHJ1Y3Qga3JlZ19yZWdpb24gKmIsCj4gKwkJCSAgY29uc3Qgc3RydWN0IGt2bV92Y3B1ICp2Y3B1 LAo+ICsJCQkgIGNvbnN0IHN0cnVjdCBrdm1fb25lX3JlZyAqcmVnKQo+ICt7Cj4gKwljb25zdCB1 bnNpZ25lZCBpbnQgdmwgPSB2Y3B1LT5hcmNoLnN2ZV9tYXhfdmw7Cj4gKwljb25zdCB1bnNpZ25l ZCBpbnQgdnEgPSBzdmVfdnFfZnJvbV92bCh2bCk7Cj4gKwo+ICsJY29uc3QgdW5zaWduZWQgaW50 IHJlZ19udW0gPQo+ICsJCShyZWctPmlkICYgU1ZFX1JFR19JRF9NQVNLKSA+PiBTVkVfUkVHX0lE X1NISUZUOwo+ICsJY29uc3QgdW5zaWduZWQgaW50IHNsaWNlX251bSA9Cj4gKwkJKHJlZy0+aWQg JiBTVkVfUkVHX1NMSUNFX01BU0spID4+IFNWRV9SRUdfU0xJQ0VfU0hJRlQ7Cj4gKwo+ICsJdW5z aWduZWQgaW50IHNsaWNlX3NpemUsIG9mZnNldCwgbGltaXQ7Cj4gKwo+ICsJaWYgKHJlZy0+aWQg Pj0gS1ZNX1JFR19BUk02NF9TVkVfWlJFRygwLCAwKSAmJgo+ICsJICAgIHJlZy0+aWQgPD0gS1ZN X1JFR19BUk02NF9TVkVfWlJFRyhTVkVfTlVNX1pSRUdTIC0gMSwKPiArCQkJCQkgICAgICBTVkVf TlVNX1NMSUNFUyAtIDEpKSB7Cj4gKwkJc2xpY2Vfc2l6ZSA9IEtWTV9SRUdfU0laRShLVk1fUkVH X0FSTTY0X1NWRV9aUkVHKDAsIDApKTsKPiArCj4gKwkJLyogQ29tcHV0ZSBzdGFydCBhbmQgZW5k IG9mIHRoZSByZWdpc3RlcjogKi8KPiArCQlvZmZzZXQgPSBTVkVfU0lHX1pSRUdfT0ZGU0VUKHZx LCByZWdfbnVtKSAtIFNWRV9TSUdfUkVHU19PRkZTRVQ7Cj4gKwkJbGltaXQgPSBvZmZzZXQgKyBT VkVfU0lHX1pSRUdfU0laRSh2cSk7Cj4gKwo+ICsJCW9mZnNldCArPSBzbGljZV9zaXplICogc2xp Y2VfbnVtOyAvKiBzdGFydCBvZiByZXF1ZXN0ZWQgc2xpY2UgKi8KPiArCj4gKwl9IGVsc2UgaWYg KHJlZy0+aWQgPj0gS1ZNX1JFR19BUk02NF9TVkVfUFJFRygwLCAwKSAmJgo+ICsJCSAgIHJlZy0+ aWQgPD0gS1ZNX1JFR19BUk02NF9TVkVfRkZSKFNWRV9OVU1fU0xJQ0VTIC0gMSkpIHsKPiArCQkv KiAoRkZSIGlzIFAxNiBmb3Igb3VyIHB1cnBvc2VzKSAqLwo+ICsKPiArCQlzbGljZV9zaXplID0g S1ZNX1JFR19TSVpFKEtWTV9SRUdfQVJNNjRfU1ZFX1BSRUcoMCwgMCkpOwo+ICsKPiArCQkvKiBD b21wdXRlIHN0YXJ0IGFuZCBlbmQgb2YgdGhlIHJlZ2lzdGVyOiAqLwo+ICsJCW9mZnNldCA9IFNW RV9TSUdfUFJFR19PRkZTRVQodnEsIHJlZ19udW0pIC0gU1ZFX1NJR19SRUdTX09GRlNFVDsKPiAr CQlsaW1pdCA9IG9mZnNldCArIFNWRV9TSUdfUFJFR19TSVpFKHZxKTsKPiArCj4gKwkJb2Zmc2V0 ICs9IHNsaWNlX3NpemUgKiBzbGljZV9udW07IC8qIHN0YXJ0IG9mIHJlcXVlc3RlZCBzbGljZSAq Lwo+ICsKPiArCX0gZWxzZSB7Cj4gKwkJcmV0dXJuIC1FTk9FTlQ7Cj4gKwl9Cj4gKwo+ICsJYi0+ a3B0ciA9IChjaGFyICopdmNwdS0+YXJjaC5zdmVfc3RhdGUgKyBvZmZzZXQ7Cj4gKwo+ICsJLyoK PiArCSAqIElmIHRoZSBzbGljZSBzdGFydHMgYWZ0ZXIgdGhlIGVuZCBvZiB0aGUgcmVnLCBqdXN0 IHBhZC4KPiArCSAqIE90aGVyd2lzZSwgY29weSBhcyBtdWNoIGFzIHBvc3NpYmxlIHVwIHRvIHNs aWNlX3NpemUgYW5kIHBhZAo+ICsJICogdGhlIHJlbWFpbmRlcjoKPiArCSAqLwo+ICsJYi0+c2l6 ZSA9IG9mZnNldCA+PSBsaW1pdCA/IDAgOiBtaW4obGltaXQgLSBvZmZzZXQsIHNsaWNlX3NpemUp Owo+ICsJYi0+emVyb3BhZCA9IHNsaWNlX3NpemUgLSBiLT5zaXplOwo+ICsKPiArCXJldHVybiAw Owo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGdldF9zdmVfcmVnKHN0cnVjdCBrdm1fdmNwdSAqdmNw dSwgY29uc3Qgc3RydWN0IGt2bV9vbmVfcmVnICpyZWcpCj4gK3sKPiArCXN0cnVjdCBrcmVnX3Jl Z2lvbiBrcmVnOwo+ICsJY2hhciBfX3VzZXIgKnVwdHIgPSAoY2hhciBfX3VzZXIgKilyZWctPmFk ZHI7Cj4gKwo+ICsJaWYgKCF2Y3B1X2hhc19zdmUodmNwdSkgfHwgc3ZlX3JlZ19yZWdpb24oJmty ZWcsIHZjcHUsIHJlZykpCj4gKwkJcmV0dXJuIC1FTk9FTlQ7Cj4gKwo+ICsJaWYgKGNvcHlfdG9f dXNlcih1cHRyLCBrcmVnLmtwdHIsIGtyZWcuc2l6ZSkgfHwKPiArCSAgICBjbGVhcl91c2VyKHVw dHIgKyBrcmVnLnNpemUsIGtyZWcuemVyb3BhZCkpCj4gKwkJcmV0dXJuIC1FRkFVTFQ7Cj4gKwo+ ICsJcmV0dXJuIDA7Cj4gK30KPiArCj4gK3N0YXRpYyBpbnQgc2V0X3N2ZV9yZWcoc3RydWN0IGt2 bV92Y3B1ICp2Y3B1LCBjb25zdCBzdHJ1Y3Qga3ZtX29uZV9yZWcgKnJlZykKPiArewo+ICsJc3Ry dWN0IGtyZWdfcmVnaW9uIGtyZWc7Cj4gKwljaGFyIF9fdXNlciAqdXB0ciA9IChjaGFyIF9fdXNl ciAqKXJlZy0+YWRkcjsKPiArCj4gKwlpZiAoIXZjcHVfaGFzX3N2ZSh2Y3B1KSB8fCBzdmVfcmVn X3JlZ2lvbigma3JlZywgdmNwdSwgcmVnKSkKPiArCQlyZXR1cm4gLUVOT0VOVDsKPiArCj4gKwlp ZiAoY29weV9mcm9tX3VzZXIoa3JlZy5rcHRyLCB1cHRyLCBrcmVnLnNpemUpKQo+ICsJCXJldHVy biAtRUZBVUxUOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICBpbnQga3ZtX2FyY2hfdmNw dV9pb2N0bF9nZXRfcmVncyhzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHN0cnVjdCBrdm1fcmVncyAq cmVncykKPiAgewo+ICAJcmV0dXJuIC1FSU5WQUw7Cj4gQEAgLTI1MSwxMiArMzc2LDExIEBAIGlu dCBrdm1fYXJtX2dldF9yZWcoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCBjb25zdCBzdHJ1Y3Qga3Zt X29uZV9yZWcgKnJlZykKPiAgCWlmICgocmVnLT5pZCAmIH5LVk1fUkVHX1NJWkVfTUFTSykgPj4g MzIgIT0gS1ZNX1JFR19BUk02NCA+PiAzMikKPiAgCQlyZXR1cm4gLUVJTlZBTDsKPgo+IC0JLyog UmVnaXN0ZXIgZ3JvdXAgMTYgbWVhbnMgd2Ugd2FudCBhIGNvcmUgcmVnaXN0ZXIuICovCj4gLQlp ZiAoKHJlZy0+aWQgJiBLVk1fUkVHX0FSTV9DT1BST0NfTUFTSykgPT0gS1ZNX1JFR19BUk1fQ09S RSkKPiAtCQlyZXR1cm4gZ2V0X2NvcmVfcmVnKHZjcHUsIHJlZyk7Cj4gLQo+IC0JaWYgKChyZWct PmlkICYgS1ZNX1JFR19BUk1fQ09QUk9DX01BU0spID09IEtWTV9SRUdfQVJNX0ZXKQo+IC0JCXJl dHVybiBrdm1fYXJtX2dldF9md19yZWcodmNwdSwgcmVnKTsKPiArCXN3aXRjaCAocmVnLT5pZCAm IEtWTV9SRUdfQVJNX0NPUFJPQ19NQVNLKSB7Cj4gKwljYXNlIEtWTV9SRUdfQVJNX0NPUkU6CXJl dHVybiBnZXRfY29yZV9yZWcodmNwdSwgcmVnKTsKPiArCWNhc2UgS1ZNX1JFR19BUk1fRlc6CXJl dHVybiBrdm1fYXJtX2dldF9md19yZWcodmNwdSwgcmVnKTsKPiArCWNhc2UgS1ZNX1JFR19BUk02 NF9TVkU6CXJldHVybiBnZXRfc3ZlX3JlZyh2Y3B1LCByZWcpOwo+ICsJfQo+Cj4gIAlpZiAoaXNf dGltZXJfcmVnKHJlZy0+aWQpKQo+ICAJCXJldHVybiBnZXRfdGltZXJfcmVnKHZjcHUsIHJlZyk7 Cj4gQEAgLTI3MCwxMiArMzk0LDExIEBAIGludCBrdm1fYXJtX3NldF9yZWcoc3RydWN0IGt2bV92 Y3B1ICp2Y3B1LCBjb25zdCBzdHJ1Y3Qga3ZtX29uZV9yZWcgKnJlZykKPiAgCWlmICgocmVnLT5p ZCAmIH5LVk1fUkVHX1NJWkVfTUFTSykgPj4gMzIgIT0gS1ZNX1JFR19BUk02NCA+PiAzMikKPiAg CQlyZXR1cm4gLUVJTlZBTDsKPgo+IC0JLyogUmVnaXN0ZXIgZ3JvdXAgMTYgbWVhbnMgd2Ugc2V0 IGEgY29yZSByZWdpc3Rlci4gKi8KPiAtCWlmICgocmVnLT5pZCAmIEtWTV9SRUdfQVJNX0NPUFJP Q19NQVNLKSA9PSBLVk1fUkVHX0FSTV9DT1JFKQo+IC0JCXJldHVybiBzZXRfY29yZV9yZWcodmNw dSwgcmVnKTsKPiAtCj4gLQlpZiAoKHJlZy0+aWQgJiBLVk1fUkVHX0FSTV9DT1BST0NfTUFTSykg PT0gS1ZNX1JFR19BUk1fRlcpCj4gLQkJcmV0dXJuIGt2bV9hcm1fc2V0X2Z3X3JlZyh2Y3B1LCBy ZWcpOwo+ICsJc3dpdGNoIChyZWctPmlkICYgS1ZNX1JFR19BUk1fQ09QUk9DX01BU0spIHsKPiAr CWNhc2UgS1ZNX1JFR19BUk1fQ09SRToJcmV0dXJuIHNldF9jb3JlX3JlZyh2Y3B1LCByZWcpOwo+ ICsJY2FzZSBLVk1fUkVHX0FSTV9GVzoJcmV0dXJuIGt2bV9hcm1fc2V0X2Z3X3JlZyh2Y3B1LCBy ZWcpOwo+ICsJY2FzZSBLVk1fUkVHX0FSTTY0X1NWRToJcmV0dXJuIHNldF9zdmVfcmVnKHZjcHUs IHJlZyk7Cj4gKwl9Cj4KPiAgCWlmIChpc190aW1lcl9yZWcocmVnLT5pZCkpCj4gIAkJcmV0dXJu IHNldF90aW1lcl9yZWcodmNwdSwgcmVnKTsKClRoZSBrZXJuZWwgY29kaW5nLXN0eWxlLnJzdCBz ZWVtcyBtdXRlIG9uIHRoZSBzdWJqZWN0IG9mIGRlZmF1bHQKaGFuZGxpbmcgaW4gc3dpdGNoIGJ1 dCBpdCdzIHByb2JhYmx5IHdvcnRoIGhhdmluZyBhOgoKICBkZWZhdWx0OiBicmVhazsgLyogZmFs bHMgdGhyb3VnaCAqLwoKdG8gYmUgZXhwbGljaXQuCgpJdCdzIG91dCBvZiBzY29wZSBmb3IgdGhp cyByZXZpZXcgYnV0IEkgZGlkIGdldCBhIGJpdCBjb25mdXNlZCBhcyB0aGUKS1ZNX1JFR19BUk1f Q09QUk9DX1NISUZUIHJlZ2lzdGVycyBzZWVtcyB0byBiZSBmYWlybHkgc3ByZWFkIG91dCBhY3Jv c3MKdGhlIGZpbGVzLiBXZSBoYXZlIGRlbXV4X2MxNV9nZXQvc2V0IGluIHN5c19yZWdzIGJ1dCBk b2Vzbid0IGxvb2sgYXMKdGhvdWdoIGl0IHRvdWNoZXMgdGhlIHJlc3Qgb2YgdGhlIGVtdWxhdGlv biBsb2dpYyBhbmQgd2UgaGF2ZQprdm1fYXJtX2dldC9zZXRfZndfcmVnIHdoaWNoIGFyZSAic3Bl Y2lhbCIgUENTSSByZWdpc3RlcnMuIEkgZ3Vlc3MgdGhpcwppcyBiZWNhdXNlIENPUFJPQ19TSElG VCBoYXMgYmVlbiB1c2VkIGZvciBhIGJ1bmNoIG9mIGRpc3BhcmF0ZSBjb3JlIGFuZApub24tY29y ZSBhbmQgc3BlY2lhbCByZWdpc3RlcnMuCgotLQpBbGV4IEJlbm7DqWUKX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18Ka3ZtYXJtIG1haWxpbmcgbGlzdAprdm1h cm1AbGlzdHMuY3MuY29sdW1iaWEuZWR1Cmh0dHBzOi8vbGlzdHMuY3MuY29sdW1iaWEuZWR1L21h aWxtYW4vbGlzdGluZm8va3ZtYXJtCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: alex.bennee@linaro.org (Alex =?utf-8?Q?Benn=C3=A9e?=) Date: Wed, 21 Nov 2018 15:20:15 +0000 Subject: [RFC PATCH v2 15/23] KVM: arm64/sve: Add SVE support to register access ioctl interface In-Reply-To: <1538141967-15375-16-git-send-email-Dave.Martin@arm.com> References: <1538141967-15375-1-git-send-email-Dave.Martin@arm.com> <1538141967-15375-16-git-send-email-Dave.Martin@arm.com> Message-ID: <87lg5mihjk.fsf@linaro.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dave Martin writes: > This patch adds the following registers for access via the > KVM_{GET,SET}_ONE_REG interface: > > * KVM_REG_ARM64_SVE_ZREG(n, i) (n = 0..31) (in 2048-bit slices) > * KVM_REG_ARM64_SVE_PREG(n, i) (n = 0..15) (in 256-bit slices) > * KVM_REG_ARM64_SVE_FFR(i) (in 256-bit slices) > > In order to adapt gracefully to future architectural extensions, > the registers are divided up into slices as noted above: the i > parameter denotes the slice index. > > For simplicity, bits or slices that exceed the maximum vector > length supported for the vcpu are ignored for KVM_SET_ONE_REG, and > read as zero for KVM_GET_ONE_REG. > > For the current architecture, only slice i = 0 is significant. The > interface design allows i to increase to up to 31 in the future if > required by future architectural amendments. > > The registers are only visible for vcpus that have SVE enabled. > They are not enumerated by KVM_GET_REG_LIST on vcpus that do not > have SVE. In all cases, surplus slices are not enumerated by > KVM_GET_REG_LIST. > > Accesses to the FPSIMD registers via KVM_REG_ARM_CORE is not > allowed for SVE-enabled vcpus: SVE-aware userspace can use the > KVM_REG_ARM64_SVE_ZREG() interface instead to access the same > register state. This avoids some complex and pointless emluation > in the kernel. > > Signed-off-by: Dave Martin > --- > > Changes since RFCv1: > > * Refactored to remove emulation of FPSIMD registers with the SVE > register view and vice-versa. This simplifies the code a fair bit. > > * Fixed a couple of range errors. > > * Inlined various trivial helpers that now have only one call site. > > * Use KVM_REG_SIZE() as a symbolic way of getting SVE register slice > sizes. > --- > arch/arm64/include/uapi/asm/kvm.h | 10 +++ > arch/arm64/kvm/guest.c | 147 ++++++++++++++++++++++++++++++++++---- > 2 files changed, 145 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index 97c3478..1ff68fa 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -226,6 +226,16 @@ struct kvm_vcpu_events { > KVM_REG_ARM_FW | ((r) & 0xffff)) > #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) > > +/* SVE registers */ > +#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) > +#define KVM_REG_ARM64_SVE_ZREG(n, i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ > + KVM_REG_SIZE_U2048 | \ > + ((n) << 5) | (i)) > +#define KVM_REG_ARM64_SVE_PREG(n, i) (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ > + KVM_REG_SIZE_U256 | \ > + ((n) << 5) | (i) | 0x400) What's the 0x400 for? Aren't PREG's already unique by being 256 bit vs the Z regs 2048 bit size? > +#define KVM_REG_ARM64_SVE_FFR(i) KVM_REG_ARM64_SVE_PREG(16, i) > + > /* Device Control API: ARM VGIC */ > #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 > #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > index 953a5c9..320db0f 100644 > > @@ -130,6 +154,107 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > return err; > } > > +struct kreg_region { > + char *kptr; > + size_t size; > + size_t zeropad; > +}; > + > +#define SVE_REG_SLICE_SHIFT 0 > +#define SVE_REG_SLICE_BITS 5 > +#define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS) > +#define SVE_REG_ID_BITS 5 > + > +#define SVE_REG_SLICE_MASK \ > + (GENMASK(SVE_REG_SLICE_BITS - 1, 0) << SVE_REG_SLICE_SHIFT) > +#define SVE_REG_ID_MASK \ > + (GENMASK(SVE_REG_ID_BITS - 1, 0) << SVE_REG_ID_SHIFT) > + I guess this all comes out in the wash once the constants are folded but GENMASK does seem to be designed for arbitrary bit positions: #define SVE_REG_SLICE_MASK \ GEN_MASK(SVE_REG_SLICE_BITS + SVE_REG_SLICE_SHIFT - 1, SVE_REG_SLICE_SHIFT) Hmm I guess that might be even harder to follow... > +#define SVE_NUM_SLICES (1 << SVE_REG_SLICE_BITS) > + > +static int sve_reg_region(struct kreg_region *b, > + const struct kvm_vcpu *vcpu, > + const struct kvm_one_reg *reg) > +{ > + const unsigned int vl = vcpu->arch.sve_max_vl; > + const unsigned int vq = sve_vq_from_vl(vl); > + > + const unsigned int reg_num = > + (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; > + const unsigned int slice_num = > + (reg->id & SVE_REG_SLICE_MASK) >> SVE_REG_SLICE_SHIFT; > + > + unsigned int slice_size, offset, limit; > + > + if (reg->id >= KVM_REG_ARM64_SVE_ZREG(0, 0) && > + reg->id <= KVM_REG_ARM64_SVE_ZREG(SVE_NUM_ZREGS - 1, > + SVE_NUM_SLICES - 1)) { > + slice_size = KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0)); > + > + /* Compute start and end of the register: */ > + offset = SVE_SIG_ZREG_OFFSET(vq, reg_num) - SVE_SIG_REGS_OFFSET; > + limit = offset + SVE_SIG_ZREG_SIZE(vq); > + > + offset += slice_size * slice_num; /* start of requested slice */ > + > + } else if (reg->id >= KVM_REG_ARM64_SVE_PREG(0, 0) && > + reg->id <= KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1)) { > + /* (FFR is P16 for our purposes) */ > + > + slice_size = KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0)); > + > + /* Compute start and end of the register: */ > + offset = SVE_SIG_PREG_OFFSET(vq, reg_num) - SVE_SIG_REGS_OFFSET; > + limit = offset + SVE_SIG_PREG_SIZE(vq); > + > + offset += slice_size * slice_num; /* start of requested slice */ > + > + } else { > + return -ENOENT; > + } > + > + b->kptr = (char *)vcpu->arch.sve_state + offset; > + > + /* > + * If the slice starts after the end of the reg, just pad. > + * Otherwise, copy as much as possible up to slice_size and pad > + * the remainder: > + */ > + b->size = offset >= limit ? 0 : min(limit - offset, slice_size); > + b->zeropad = slice_size - b->size; > + > + return 0; > +} > + > +static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > +{ > + struct kreg_region kreg; > + char __user *uptr = (char __user *)reg->addr; > + > + if (!vcpu_has_sve(vcpu) || sve_reg_region(&kreg, vcpu, reg)) > + return -ENOENT; > + > + if (copy_to_user(uptr, kreg.kptr, kreg.size) || > + clear_user(uptr + kreg.size, kreg.zeropad)) > + return -EFAULT; > + > + return 0; > +} > + > +static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > +{ > + struct kreg_region kreg; > + char __user *uptr = (char __user *)reg->addr; > + > + if (!vcpu_has_sve(vcpu) || sve_reg_region(&kreg, vcpu, reg)) > + return -ENOENT; > + > + if (copy_from_user(kreg.kptr, uptr, kreg.size)) > + return -EFAULT; > + > + return 0; > +} > + > int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) > { > return -EINVAL; > @@ -251,12 +376,11 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32) > return -EINVAL; > > - /* Register group 16 means we want a core register. */ > - if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) > - return get_core_reg(vcpu, reg); > - > - if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW) > - return kvm_arm_get_fw_reg(vcpu, reg); > + switch (reg->id & KVM_REG_ARM_COPROC_MASK) { > + case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg); > + case KVM_REG_ARM_FW: return kvm_arm_get_fw_reg(vcpu, reg); > + case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg); > + } > > if (is_timer_reg(reg->id)) > return get_timer_reg(vcpu, reg); > @@ -270,12 +394,11 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32) > return -EINVAL; > > - /* Register group 16 means we set a core register. */ > - if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) > - return set_core_reg(vcpu, reg); > - > - if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_FW) > - return kvm_arm_set_fw_reg(vcpu, reg); > + switch (reg->id & KVM_REG_ARM_COPROC_MASK) { > + case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg); > + case KVM_REG_ARM_FW: return kvm_arm_set_fw_reg(vcpu, reg); > + case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg); > + } > > if (is_timer_reg(reg->id)) > return set_timer_reg(vcpu, reg); The kernel coding-style.rst seems mute on the subject of default handling in switch but it's probably worth having a: default: break; /* falls through */ to be explicit. It's out of scope for this review but I did get a bit confused as the KVM_REG_ARM_COPROC_SHIFT registers seems to be fairly spread out across the files. We have demux_c15_get/set in sys_regs but doesn't look as though it touches the rest of the emulation logic and we have kvm_arm_get/set_fw_reg which are "special" PCSI registers. I guess this is because COPROC_SHIFT has been used for a bunch of disparate core and non-core and special registers. -- Alex Benn?e