Re: [Qemu-devel] [RFC] translate-all: protect code_gen_buffer with RCU

["Alex Bennée" <alex.bennee@linaro.org>]

Emilio G. Cota <cota@braap.org> writes:

> On Fri, Apr 22, 2016 at 15:41:13 +0100, Alex Bennée wrote:
>> Emilio G. Cota <cota@braap.org> writes:
> (snip)
>> > Known issues:
>> > - Basically compile-tested only, since I've only run this with
>> >   single-threaded TCG; I also tried running it with linux-user,
>> >   but in order to trigger tb_flush I had to make code_gen_buffer
>> >   so small that the CPU calling tb_flush would immediately fill
>> >   the 2nd buffer, triggering the assert. If you have a working
>> >   multi-threaded workload that would be good to test this, please
>> >   let me know.
>>
>> With my latest mttcg unit tests:
>>
>> ./arm-softmmu/qemu-system-arm -machine virt,accel=tcg -cpu cortex-a15 \
>>   -device virtio-serial-device -device virtconsole,chardev=ctd \
>>   -chardev testdev,id=ctd -display none -serial stdio \
>>   -kernel arm/tcg-test.flat -smp 4 -tcg mttcg=on \
>>   -append "tight smc irq mod=1 rounds=100000"  -name arm,debug-threads=on
>
> This is useful. Never mind the need for testing linux-user, I can test
> both code paths (i.e. dynamic allocation and static buf) with qemu-system
> by simply defining USE_STATIC_CODE_GEN_BUFFER.
>
> After applying a modified version of this patch (that I'll send in
> a jiffy) to your enable-mttcg-for-armv7-v1 branch (reverting first
> "translate-all: introduces tb_flush_safe"), I can easily trigger
> this error when setting a low enough TB size, e.g. -tb-size 32:
>
>  CPU1: online and setting up with pattern 0xa0b78cbf
>  CPU2: online and setting up with pattern 0x22287c45
>  CPU3: online and setting up with pattern 0x6262c5c5
>  CPU0: online and setting up with pattern 0xa65e7ad6
>  qemu: flush code_size=10622184 nb_tbs=83886 avg_tb_size=126
>  qemu: flush code_size=10469016 nb_tbs=83886 avg_tb_size=124
>  qemu: flush code_size=10492920 nb_tbs=83886 avg_tb_size=125
>  qemu: flush code_size=10477464 nb_tbs=83886 avg_tb_size=124
>  qemu: flush code_size=10495800 nb_tbs=83886 avg_tb_size=125
>  PASS: smc: irq: 0 errors, IRQs not checked
>  Unhandled exception 3 (pabt)
>  Exception frame registers:
>  pc : [<e59f2028>]    lr : [<40010700>]    psr: a0000153
>  sp : 400ac5c0  ip : 400ab4e8  fp : 40032ca8
>  r10: 00000000  r9 : 00000000  r8 : 00000000
>  r7 : 00000000  r6 : 00000000  r5 : 00000000  r4 : 00000000
>  r3 : 00000000  r2 : 00000000  r1 : e59f2028  r0 : 00000000
>  Flags: NzCv  IRQs on  FIQs off  Mode SVC_32
>  Control: 00c5107d  Table: 40060000  DAC: 00000000
>  IFAR: e59f2028    IFSR: 00000205
>
> Any input on where to look would be appreciated. Thanks,

I'll have a look and see if I can replicate.

>
> 		Emilio


--
Alex Bennée