Re: Pegatron BYT-T1 eDP/LVDS resolution problem (VBT vs EDID)

From: Jani Nikula <jani.nikula@linux.intel.com>
To: Edgardo Gho <edgardo.g@telikin.com>, intel-gfx@lists.freedesktop.org
Subject: Re: Pegatron BYT-T1 eDP/LVDS resolution problem (VBT vs	EDID)
Date: Thu, 18 Jun 2015 09:44:45 +0300	[thread overview]
Message-ID: <87lhfhikgy.fsf@intel.com> (raw)
In-Reply-To: <5581E332.7080908@telikin.com>

On Thu, 18 Jun 2015, Edgardo Gho <edgardo.g@telikin.com> wrote:
> Hi,
> I have an AIO computer with a Pegatron BYT-T1 motherboard. Looks like a 
> cheap motherboard (using J1900).
> It has an innolux 1366x768 panel (LVDS). The Motherboard also has LVDS 
> written on the connector.
> I'm running kernel 4.0.5 on it (tinycore custom kernel) and xrandr 
> displays the port as eDP1 (not LVDS).
>  From what I can tell the panel is LVDS so I'm a little confused why the 
> kernel picks it up as eDP. The CPU is valleyview.

This would be because BYT does not have LVDS, and apparently your
motherboard has an eDP->LVDS adapter.

> The problem I have is this:
> When drm/i915 reads the EDID on eDP1, it gets a bunch of stuff 
> (including 1920x1080) and sets the resolution to that.
> But the panel supports 1366x768 as max. That seems to be saved on VBT 
> since if I use vga=0x37f I get 1366x768 on fb.
> But when drm reads 1920x1080 from EDID it sets that and the panel goes 
> into a weird mode (displaying colors) which I believe is a testing mode.
>
> I could try to fix the EDID, and also could generate one and use the 
> drm_kms_helper to pass a binary EDID.
> What I don't understand is where is this EDID coming from. LVDS supports 
> EDID read? I don't see any i2c cable on the LVDS cable so I don't 
> understand how it can be reading the EDID.
> Is the EDID saved on BIOS somehow?

I assume the eDP->LVDS adapter responds to the EDID reads. The problem
is, apparently it reports a preferred mode that the LVDS does not
support, and our driver insists on using only the preferred mode for
eDP.

> I changed the code as suggested by this thread:
> VLV: eDP: panel timings / resolution data from VBT,    not via i2c from 
> eDP EDID
> http://www.spinics.net/lists/intel-gfx/msg64312.html
>
> and I'm not letting edp read the EDID, so it fallbacks to VBT and 
> everything works great.
> But I'm still not convinced that the EDID data comes from the LVDS Panel 
> (since it should have different info)
>
> Hope anyone can share some insights on what is going on.
> Thanks

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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