From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: Re: [PATCH 2/2] drm/i915: Correct the bit number for the MI_FLUSH_ENABLE. Date: Wed, 25 Jan 2012 10:31:39 -0800 Message-ID: <87liovd46s.fsf@eliezer.anholt.net> References: <1326999006-15100-1-git-send-email-eric@anholt.net> <1326999006-15100-2-git-send-email-eric@anholt.net> <20120121163613.GE3821@phenom.ffwll.local> <87vco0cwxy.fsf@eliezer.anholt.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0543863973==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0543863973== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha1; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Wed, 25 Jan 2012 09:57:58 +0000, Chris Wilson = wrote: > On Tue, 24 Jan 2012 18:55:53 -0800, Eric Anholt wrote: > > On Sat, 21 Jan 2012 17:36:13 +0100, Daniel Vetter wro= te: > > > On Thu, Jan 19, 2012 at 10:50:06AM -0800, Eric Anholt wrote: > > > > Older specs claimed this was bit 11, but newer specs and the actual > > > > simulator code say it was bit 12. Regardless, we don't use MI_FLUS= H, > > > > or try to enable it any more. > > > >=20 > > > > Signed-off-by: Eric Anholt > > >=20 > > > I'd like to amend this with the following (on this patch instead of t= he > > > other, so that ppl actually can find it with git blame): > > >=20 > > > "Furthermore actually setting bit12 results in gpu hangs both on snb = and > > > ivb. Ben Widawsky discovered a ppt that claims that both bit12 and bi= t11 > > > must be set, but that doesn't help either. And last but not least, > > > MI_FLUSH seems to work regardless of the setting of these bits." > >=20 > > I haven't seen bit12 hanging snb/ivb -- I only knew of it hanging ilk > > (since it doesn't exist there). On my snb, running xvideo so that > > MI_FLUSHes are generated by the userland (I think -- I haven't caught > > them in cat i915_batchbuffers | intel_dump_decode -), with > > intel_reg_read 0x209c saying 0x1240, things are going fine. Also with > > 0x209c saying 0x240 (the result of this patch). >=20 > The SNB Xv path, that is the code called by Gen6DisplayVideoTexture,=20 > never used MI_FLUSH. Oops. Not sure why I remembered confirming that that code still MI_FLUSHed on newer chipsets. --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iEYEARECAAYFAk8gSosACgkQHUdvYGzw6vciLwCeOea1P8z34Bp2FMkgGAxf+RGt mVIAoIDJ5LHHyMxs40uansA5sfinaE38 =4Stp -----END PGP SIGNATURE----- --=-=-=-- --===============0543863973== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0543863973==--