Re: [PATCH 1/4] dt-bindings: mtd: qcom,nandc: Add MDM9607 QPIC NAND controller

From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Stephan Gerhold <stephan.gerhold@linaro.org>,
	 Manivannan Sadhasivam <mani@kernel.org>,
	 Richard Weinberger <richard@nod.at>,
	 Vignesh Raghavendra <vigneshr@ti.com>,
	 Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	linux-mtd@lists.infradead.org,  linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: mtd: qcom,nandc: Add MDM9607 QPIC NAND controller
Date: Tue, 09 Jun 2026 09:52:51 +0200	[thread overview]
Message-ID: <87mrx4b164.fsf@bootlin.com> (raw)
In-Reply-To: <20260609-quirky-rat-of-criticism-aea1fe@quoll> (Krzysztof Kozlowski's message of "Tue, 9 Jun 2026 09:19:52 +0200")

Hello,

>> On MDM9607, there is only a single controllable clock for the NAND
>> controller (RPM_SMD_QPIC_CLK). The same situation also applies e.g. for
>> qcom,sdx55-nand, but the corresponding device tree (qcom-sdx55.dtsi) works
>> around that by assigning a dummy clock (&nand_clk_dummy) to the second
>> clock ("aon") that is required by the dt-bindings. This is not really
>> useful, so avoid doing that for new platforms by excluding the second "aon"
>> clock entry in the dt-bindings.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

What is the problem in giving twice the same clock? If this is what is
done in the hardware routing, I do not see the reason for more
complexity in the binding?

Thanks,
Miquèl