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Wed, 27 May 2026 05:58:41 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490454ac676sm429859485e9.13.2026.05.27.05.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2026 05:58:40 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 93D9E5F7F0; Wed, 27 May 2026 13:58:39 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Torbjorn SVENSSON Cc: , , Peter Maydell , Richard Henderson Subject: Re: [PING] [PATCH 0/3] target/arm: add support for Cortex-M pointer authentication code In-Reply-To: (Torbjorn SVENSSON's message of "Wed, 27 May 2026 09:36:03 +0200") References: <20260518-pr-pacbti-v1-0-8932a885b03d@foss.st.com> User-Agent: mu4e 1.14.1; emacs 30.1 Date: Wed, 27 May 2026 13:58:39 +0100 Message-ID: <87mrxlxb40.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Torbjorn SVENSSON writes: > Gentle ping! :) > > There is apparently also a ticket for this work (that I did not see befor= e I sent the patches): https://linaro.atlassian.net/browse/QEMU-444 > The Linaro tickets are public (because we work directly upstream) although the existence of a ticket should not imply that we plan to work on it. We create tickets for most of the Arm CPU features so we can track dependencies, what is left to do and when others have patches that need review. Our actual planned roadmap can be seen here: https://linaro.atlassian.net/w= iki/spaces/QEMU/overview > > On 2026-05-18 18:13, Torbj=C3=B6rn SVENSSON wrote: >> Testing an arm-none-eabi GCC toolchain using QEMU gives unpredictable >> test results for some test cases. In the GCC testsuite function >> check_effective_target_arm_pacbti_hw, the testsuite tries to identify >> if the target supports PACBTI instructions. The test consists of: >> __attribute__ ((naked)) int >> main (void) >> { >> asm ("pac r12, lr, sp"); >> asm ("mov r0, #0"); >> asm ("autg r12, lr, sp"); >> asm ("bx lr"); >> } >> Running the above code in QEMU will cause LR to get corrupted. >> The reson for the corruption is that AUTG overlaps with the SMMLA >> instruction, and SMMLA will write the result to Rn, that for >> `AUTG R12, LR, SP` happens to match `LR`. > > The above statement is not entirely true. > SMMLA is writing the result to Rd and that happens to match PC, not Rn an= d LR. > Sorry for the confusion this might have caused. > > Kind regards, > Torbj=C3=B6rn > >> The solution to the above problem is to define the following new >> Cortex-M instructions in QEMU: >> * AUT >> * AUTG >> * BXAUT >> * PAC >> * PACBTI >> * PACG >> This patch series only implements the pointer authentication code >> part >> of PACBTI. The branch target identification part is not implemented. >> Signed-off-by: Torbj=C3=B6rn SVENSSON >> --- >> Torbj=C3=B6rn SVENSSON (3): >> target/arm/tcg: define cortex-m85 cpu >> target/arm/tcg: add PAC related instructions >> target/arm: implement v8.1-m PAC support >> target/arm/cpu-features.h | 6 ++ >> target/arm/internals.h | 2 + >> target/arm/tcg/cpu-v7m.c | 40 +++++++++++++ >> target/arm/tcg/m_helper.c | 17 ++++++ >> target/arm/tcg/t32.decode | 21 ++++++- >> target/arm/tcg/translate.c | 138 +++++++++++++++++++++++++++++++++++++= ++++++++ >> 6 files changed, 221 insertions(+), 3 deletions(-) >> --- >> base-commit: ac6721b88df944ade0048822b2b74210f543d656 >> change-id: 20260518-pr-pacbti-366d7acbe1be >> Best regards, --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro