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Thu, 21 May 2026 07:55:58 -0700 (PDT) Received: from draig.lan ([185.124.0.195]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4903cadc03esm29445545e9.9.2026.05.21.07.55.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2026 07:55:57 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id AE3A15F886; Thu, 21 May 2026 15:55:56 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: Re: [PATCH 2/3] target/arm: Use FPST_A64_F16 for SVE FCVTLT_hs In-Reply-To: <20260521122913.1565011-3-peter.maydell@linaro.org> (Peter Maydell's message of "Thu, 21 May 2026 13:29:12 +0100") References: <20260521122913.1565011-1-peter.maydell@linaro.org> <20260521122913.1565011-3-peter.maydell@linaro.org> User-Agent: mu4e 1.14.1; emacs 30.1 Date: Thu, 21 May 2026 15:55:56 +0100 Message-ID: <87mrxsolqb.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > The SVE FCVTLT_hs operation produces a halfprec result, so we should > use the FPST_A64_F16 fpstatus for it. Maybe I'm reading the Arm ARM wrong (I can't find FCVTLT_hs but I can see FCVTLT in the SVE encodings). But these are all widening operations so I can see halfprec to single, not the other way around. > Getting this wrong means we > will incorrectly set FPCR.IDC for input-denormals when FPCR.AH=3D1. > > We missed this instruction when we updated the halfproc-to-other > conversion insns to use FPST_A64_F16 in commit e07b48995aaa > as part of implementing FEAT_AHP. > > Cc: qemu-stable@nongnu.org > Fixes: e07b48995aaa ("target/arm: Use FPST_A64_F16 for halfprec-to-other = conversions")a > Signed-off-by: Peter Maydell > --- > target/arm/tcg/translate-sve.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sv= e.c > index bf9f0ae179..59b8c494a8 100644 > --- a/target/arm/tcg/translate-sve.c > +++ b/target/arm/tcg/translate-sve.c > @@ -7827,7 +7827,7 @@ TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fps= t_arg_zpz, > s->fpcr_ah ? FPST_AH : FPST_A64) >=20=20 > TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, > - gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64) > + gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64_F16) > TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, > gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro