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Thu, 21 Aug 2025 15:59:07 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c6639bf1-7ea7-11f0-b898-0df219b8e170 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ndP1wtsdpyWuIM8MHfIcjGYiT/gZ4rJQ4zezvX0FCo6fLLOYywxeAuTCqdIJJgfJvpxp+ePXmFTkZCma8hd4leAa63P7q1oAvQ0+kZtZb25JF+C17mYWW2nAmawFC5DV/LGoCN35m7FkklmKyrIfW8pWCaR4RpBk7CQPGu+IA7V/MZ1GB/1BNxO1dsRqB9U2IxiIZNQHFUSGVgXHpjEodpg4/aI8G8TBMLYNRqIwGrLOTdLvrLirSalo9WG2qqSWTZTnb5DnpVaCw0MzzvlPi393xQ4NL0JMrRK6oT9nWiYw78MLEXwo11l+miaNFCYwB6LbTbv/YEwl+CoW8q2RBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV1PR03MB10456.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a0fe37d1-2a56-42db-4ada-08dde0cba8d7 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Aug 2025 15:59:07.1877 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: M1H5QXuStVs5TZEZLCAN2Qj4Vq0QNRJezCIDKWCjwLrOQUvSvPKpsXM03XBzPMnyR2xuuspgXKrkrS/EhgRTdNTiwET8cexpDVNDB7ZhMDo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR03MB7146 Leonid Komarianskyi writes: > Currently, Xen does not support eSPI interrupts, leading > to a data abort when such interrupts are defined in the DTS. > > This patch introduces a separate array to initialize up to > 1024 interrupt descriptors in the eSPI range and adds the > necessary defines and helper function. These changes lay the > groundwork for future implementation of full eSPI interrupt > support. As this GICv3.1 feature is not required by all vendors, > all changes are guarded by ifdefs, depending on the corresponding > Kconfig option. I don't think that it is a good idea to hide this feature under Kconfig option, as this will increase number of different build variants. I believe that runtime check for GICD_TYPER.ESPI should be sufficient, but maintainers can correct me there. > > Signed-off-by: Leonid Komarianskyi > > --- > Changes in V2: > - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS) > - remove unnecessary comment for nr_irqs initialization > --- > xen/arch/arm/Kconfig | 9 +++++++++ > xen/arch/arm/include/asm/irq.h | 25 +++++++++++++++++++++++++ > xen/arch/arm/irq.c | 26 ++++++++++++++++++++++++++ > 3 files changed, 60 insertions(+) > > diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig > index 17df147b25..08073ece1f 100644 > --- a/xen/arch/arm/Kconfig > +++ b/xen/arch/arm/Kconfig > @@ -135,6 +135,15 @@ config GICV3 > Driver for the ARM Generic Interrupt Controller v3. > If unsure, use the default setting. > =20 > +config GICV3_ESPI > + bool "Extended SPI range support" > + depends on GICV3 && !NEW_VGIC > + default y > + help > + Allow Xen and domains to use interrupt numbers from the extended SPI > + range, from 4096 to 5119. This feature is introduced in GICv3.1 > + architecture. > + > config HAS_ITS > bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPO= RTED > depends on GICV3 && !NEW_VGIC && !ARM_32 > diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir= q.h > index 5bc6475eb4..acebc3d42f 100644 > --- a/xen/arch/arm/include/asm/irq.h > +++ b/xen/arch/arm/include/asm/irq.h > @@ -32,6 +32,14 @@ struct arch_irq_desc { > #define SPI_MAX_INTID 1019 > #define LPI_OFFSET 8192 > =20 > +#ifdef CONFIG_GICV3_ESPI > +#define ESPI_BASE_INTID 4096 > +#define ESPI_MAX_INTID 5119 > + > +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID) > +#define ESPI_IDX2INTID(idx) ((idx) + ESPI_BASE_INTID) > +#endif > + > /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas= e. */ > #define INVALID_LPI 0 > =20 > @@ -39,7 +47,15 @@ struct arch_irq_desc { > #define INVALID_IRQ 1023 > =20 > extern const unsigned int nr_irqs; > +#ifdef CONFIG_GICV3_ESPI > +/* > + * This will also cover the eSPI range, as some critical devices > + * for booting Xen (e.g., serial) may use this type of interrupts. > + */ > +#define nr_static_irqs (ESPI_MAX_INTID + 1) > +#else > #define nr_static_irqs NR_IRQS > +#endif Don't introduce defines that look like variables. I am sure that MISRA team will be unhappy about that. But what you can really do is to introduce variable nr_static_irqs, which value will depend on GICD_TYPER.ESPI and GICD_TYPER.ESPI_range > =20 > struct irq_desc; > struct irqaction; > @@ -55,6 +71,15 @@ static inline bool is_lpi(unsigned int irq) > return irq >=3D LPI_OFFSET; > } > =20 > +static inline bool is_espi(unsigned int irq) > +{ > +#ifdef CONFIG_GICV3_ESPI > + return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID); > +#else > + return false; > +#endif > +} > + > #define domain_pirq_to_irq(d, pirq) (pirq) > =20 > bool is_assignable_irq(unsigned int irq); > diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c > index 50e57aaea7..9bc72fbbc9 100644 > --- a/xen/arch/arm/irq.c > +++ b/xen/arch/arm/irq.c > @@ -19,7 +19,11 @@ > #include > #include > =20 > +#ifdef CONFIG_GICV3_ESPI > +const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1; > +#else > const unsigned int nr_irqs =3D NR_IRQS; > +#endif > =20 > static unsigned int local_irqs_type[NR_LOCAL_IRQS]; > static DEFINE_SPINLOCK(local_irqs_type_lock); > @@ -46,6 +50,9 @@ void irq_end_none(struct irq_desc *irq) > } > =20 > static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS]; > +#ifdef CONFIG_GICV3_ESPI > +static irq_desc_t espi_desc[NR_IRQS]; This is really confusing. Should it be something like espi_desc[NR_ESPI_IRQ= S]? > +#endif > static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc); > =20 > struct irq_desc *__irq_to_desc(unsigned int irq) > @@ -53,6 +60,11 @@ struct irq_desc *__irq_to_desc(unsigned int irq) > if ( irq < NR_LOCAL_IRQS ) > return &this_cpu(local_irq_desc)[irq]; > =20 > +#ifdef CONFIG_GICV3_ESPI > + if ( is_espi(irq) ) > + return &espi_desc[ESPI_INTID2IDX(irq)]; > +#endif > + > return &irq_desc[irq-NR_LOCAL_IRQS]; > } > =20 > @@ -79,6 +91,20 @@ static int __init init_irq_data(void) > desc->action =3D NULL; > } > =20 > +#ifdef CONFIG_GICV3_ESPI > + for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ ) > + { > + struct irq_desc *desc =3D irq_to_desc(irq); > + int rc =3D init_one_irq_desc(desc); > + > + if ( rc ) > + return rc; > + > + desc->irq =3D irq; > + desc->action =3D NULL; > + } > +#endif > + > return 0; > } --=20 WBR, Volodymyr=