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22 Mar 2024 08:07:36 -0700 From: Jani Nikula To: Lucas De Marchi , intel-xe@lists.freedesktop.org Subject: Re: [PATCH] drm/xe: Fix END redefinition In-Reply-To: <20240322145037.196548-1-lucas.demarchi@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20240322145037.196548-1-lucas.demarchi@intel.com> Date: Fri, 22 Mar 2024 17:07:31 +0200 Message-ID: <87msqqjoek.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, 22 Mar 2024, Lucas De Marchi wrote: > mips declares an END macro in its headers so it can't be used without > namespace in a driver like xe. > > Instead of coming up with a longer name, just remove the macro and > replace its use with 0 since it's still clear what that means: > set_offsets() was already using that implicitly when checking the data > variable. > > Closes: http://kisskb.ellerman.id.au/kisskb/buildresult/15143996/ > Reported-by: Guenter Roeck > Tested-by: Guenter Roeck > Signed-off-by: Lucas De Marchi Reviewed-by: Jani Nikula > --- > > Complete series that needs closer scrutiny: > https://lore.kernel.org/intel-xe/20240321221726.102193-1-lucas.demarchi@intel.com/ > > Sending this by itself for CI coverage. > > drivers/gpu/drm/xe/xe_lrc.c | 20 +++++++++----------- > 1 file changed, 9 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c > index 8c85e90220de..2bbf008b83ff 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.c > +++ b/drivers/gpu/drm/xe/xe_lrc.c > @@ -97,7 +97,6 @@ static void set_offsets(u32 *regs, > #define REG16(x) \ > (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ > (((x) >> 2) & 0x7f) > -#define END 0 > { > const u32 base = hwe->mmio_base; > > @@ -168,7 +167,7 @@ static const u8 gen12_xcs_offsets[] = { > REG16(0x274), > REG16(0x270), > > - END > + 0 > }; > > static const u8 dg2_xcs_offsets[] = { > @@ -202,7 +201,7 @@ static const u8 dg2_xcs_offsets[] = { > REG16(0x274), > REG16(0x270), > > - END > + 0 > }; > > static const u8 gen12_rcs_offsets[] = { > @@ -298,7 +297,7 @@ static const u8 gen12_rcs_offsets[] = { > REG(0x084), > NOP(1), > > - END > + 0 > }; > > static const u8 xehp_rcs_offsets[] = { > @@ -339,7 +338,7 @@ static const u8 xehp_rcs_offsets[] = { > LRI(1, 0), > REG(0x0c8), > > - END > + 0 > }; > > static const u8 dg2_rcs_offsets[] = { > @@ -382,7 +381,7 @@ static const u8 dg2_rcs_offsets[] = { > LRI(1, 0), > REG(0x0c8), > > - END > + 0 > }; > > static const u8 mtl_rcs_offsets[] = { > @@ -425,7 +424,7 @@ static const u8 mtl_rcs_offsets[] = { > LRI(1, 0), > REG(0x0c8), > > - END > + 0 > }; > > #define XE2_CTX_COMMON \ > @@ -471,7 +470,7 @@ static const u8 xe2_rcs_offsets[] = { > LRI(1, 0), /* [0x47] */ > REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */ > > - END > + 0 > }; > > static const u8 xe2_bcs_offsets[] = { > @@ -482,16 +481,15 @@ static const u8 xe2_bcs_offsets[] = { > REG16(0x200), /* [0x42] BCS_SWCTRL */ > REG16(0x204), /* [0x44] BLIT_CCTL */ > > - END > + 0 > }; > > static const u8 xe2_xcs_offsets[] = { > XE2_CTX_COMMON, > > - END > + 0 > }; > > -#undef END > #undef REG16 > #undef REG > #undef LRI -- Jani Nikula, Intel