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From: Jani Nikula <jani.nikula@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, ankit.k.nautiyal@intel.com,
	Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Subject: Re: [PATCH v12 2/8] drm: Add Adaptive Sync SDP logging
Date: Thu, 29 Feb 2024 12:37:38 +0200	[thread overview]
Message-ID: <87msrj8sjx.fsf@intel.com> (raw)
In-Reply-To: <20240228143823.2762595-3-mitulkumar.ajitkumar.golani@intel.com>

On Wed, 28 Feb 2024, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> Add structure representing Adaptive Sync Secondary Data Packet (AS SDP).
> Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate
> debugging.

To be honest, the division of patches is a bit weird. There's no reason
to change i915 here, is there?

> --v2:
> - Update logging. [Jani, Ankit]
> - Use 'as_sdp' instead of 'async' [Ankit]
> - Correct define placeholders to where they are actually used. [Jani]
> - Update members in 'as_sdp' structure to make it uniform. [Jani]
>
> --v3:
> - Added changes to dri-devel mailing list. No code changes.
>
> --v4:
> - Instead of directly using operation mode, use an enum to accommodate
> all operation modes (Ankit).
>
> --v5:
> Nit-pick changes to commit message.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_helper.c       | 12 +++++++
>  .../drm/i915/display/intel_crtc_state_dump.c  | 12 +++++++
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  include/drm/display/drm_dp.h                  |  9 +++++
>  include/drm/display/drm_dp_helper.h           | 33 +++++++++++++++++++
>  5 files changed, 67 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
> index f94c04db7187..b1459ac92aea 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2913,6 +2913,18 @@ void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
>  }
>  EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
>  
> +void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
> +{
> +	drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n",
> +		   as_sdp->revision, as_sdp->length);
> +	drm_printf(p, "    vtotal: %d\n", as_sdp->vtotal);
> +	drm_printf(p, "    target_rr: %d\n", as_sdp->target_rr);
> +	drm_printf(p, "    duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
> +	drm_printf(p, "    duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
> +	drm_printf(p, "    operation_mode: %d\n", as_sdp->mode);
> +}
> +EXPORT_SYMBOL(drm_dp_as_sdp_log);
> +
>  /**
>   * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
>   * @aux: DisplayPort AUX channel
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 4bcf446c75f4..26d77c2934e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -60,6 +60,15 @@ intel_dump_dp_vsc_sdp(struct drm_i915_private *i915,
>  	drm_dp_vsc_sdp_log(&p, vsc);
>  }
>  
> +static void
> +intel_dump_dp_as_sdp(struct drm_i915_private *i915,
> +		     const struct drm_dp_as_sdp *as_sdp)
> +{
> +	struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "AS_SDP");
> +
> +	drm_dp_as_sdp_log(&p, as_sdp);
> +}
> +
>  static void
>  intel_dump_buffer(struct drm_i915_private *i915,
>  		  const char *prefix, const u8 *buf, size_t len)
> @@ -299,6 +308,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>  		intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
> +		intel_dump_dp_as_sdp(i915, &pipe_config->infoframes.as_sdp);
>  	if (pipe_config->infoframes.enable &
>  	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
>  		intel_dump_dp_vsc_sdp(i915, &pipe_config->infoframes.vsc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8ce986fadd9a..1256730ea276 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1335,6 +1335,7 @@ struct intel_crtc_state {
>  		union hdmi_infoframe hdmi;
>  		union hdmi_infoframe drm;
>  		struct drm_dp_vsc_sdp vsc;
> +		struct drm_dp_as_sdp as_sdp;
>  	} infoframes;
>  
>  	u8 eld[MAX_ELD_BYTES];
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index 281afff6ee4e..0601b95d53db 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1578,10 +1578,12 @@ enum drm_dp_phy {
>  #define DP_SDP_AUDIO_COPYMANAGEMENT	0x05 /* DP 1.2 */
>  #define DP_SDP_ISRC			0x06 /* DP 1.2 */
>  #define DP_SDP_VSC			0x07 /* DP 1.2 */
> +#define DP_SDP_ADAPTIVE_SYNC		0x22 /* DP 1.4 */
>  #define DP_SDP_CAMERA_GENERIC(i)	(0x08 + (i)) /* 0-7, DP 1.3 */
>  #define DP_SDP_PPS			0x10 /* DP 1.4 */
>  #define DP_SDP_VSC_EXT_VESA		0x20 /* DP 1.4 */
>  #define DP_SDP_VSC_EXT_CEA		0x21 /* DP 1.4 */
> +
>  /* 0x80+ CEA-861 infoframe types */
>  
>  #define DP_SDP_AUDIO_INFOFRAME_HB2	0x1b
> @@ -1737,4 +1739,11 @@ enum dp_content_type {
>  	DP_CONTENT_TYPE_GAME = 0x04,
>  };
>  
> +enum operation_mode {
> +	DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
> +	DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
> +	DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,
> +	DP_AS_SDP_FAVT_TRR_REACHED = 0x03
> +};
> +
>  #endif /* _DRM_DP_H_ */
> diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
> index 7c1aa3a703c8..7b7729488ad8 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -98,6 +98,37 @@ struct drm_dp_vsc_sdp {
>  	enum dp_content_type content_type;
>  };
>  
> +/**
> + * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
> + *
> + * This structure represents a DP AS SDP of drm
> + * It is based on DP 2.1 spec [Table 2-126:  Adaptive-Sync SDP Header Bytes] and
> + * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
> + *
> + * @sdp_type: Secondary-data packet type
> + * @revision: Revision Number
> + * @length: Number of valid data bytes
> + * @vtotal: Minimum Vertical Vtotal
> + * @target_rr: Target Refresh
> + * @duration_incr_ms: Successive frame duration increase
> + * @duration_decr_ms: Successive frame duration decrease
> + * @operation_mode: Adaptive Sync Operation Mode
> + */
> +

Superfluous newline.

> +struct drm_dp_as_sdp {
> +	unsigned char sdp_type;
> +	unsigned char revision;
> +	unsigned char length;
> +	int vtotal;
> +	int target_rr;
> +	int duration_incr_ms;
> +	int duration_decr_ms;
> +	enum operation_mode mode;
> +};
> +
> +void drm_dp_as_sdp_log(struct drm_printer *p,
> +		       const struct drm_dp_as_sdp *as_sdp);
> +
>  void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
>  
>  bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> @@ -810,6 +841,8 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
>  #define DRM_DP_BW_OVERHEAD_FEC		BIT(3)
>  #define DRM_DP_BW_OVERHEAD_DSC		BIT(4)
>  
> +#define AS_SDP_OP_MODE			GENMASK(1, 0)

Oddly placed, oddly named.

> +
>  int drm_dp_bw_overhead(int lane_count, int hactive,
>  		       int dsc_slice_count,
>  		       int bpp_x16, unsigned long flags);

-- 
Jani Nikula, Intel

  parent reply	other threads:[~2024-02-29 10:37 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-28 14:38 [PATCH v12 0/8] Enable Adaptive Sync SDP Support for DP Mitul Golani
2024-02-28 14:38 ` [PATCH v12 1/8] drm/dp: Add support to indicate if sink supports AS SDP Mitul Golani
2024-02-29 10:01   ` Nautiyal, Ankit K
2024-02-28 14:38 ` [PATCH v12 2/8] drm: Add Adaptive Sync SDP logging Mitul Golani
2024-02-29 10:07   ` Nautiyal, Ankit K
2024-02-29 11:23     ` Jani Nikula
2024-02-29 12:13       ` Nautiyal, Ankit K
2024-02-29 10:37   ` Jani Nikula [this message]
2024-02-29 16:33     ` Golani, Mitulkumar Ajitkumar
2024-02-29 19:30       ` Jani Nikula
2024-02-29 19:53         ` Golani, Mitulkumar Ajitkumar
2024-02-28 14:38 ` [PATCH v12 3/8] drm/i915/dp: Add Read/Write support for Adaptive Sync SDP Mitul Golani
2024-02-29 10:28   ` Nautiyal, Ankit K
2024-02-28 14:38 ` [PATCH v12 4/8] drm/i915/display/dp: Add wrapper function to check AS SDP Mitul Golani
2024-02-29 10:30   ` Nautiyal, Ankit K
2024-02-28 14:38 ` [PATCH v12 5/8] drm/i915/display: Compute AS SDP parameters Mitul Golani
2024-02-29 11:07   ` Nautiyal, Ankit K
2024-02-28 14:38 ` [PATCH v12 6/8] drm/i915/display: Add state checker for Adaptive Sync SDP Mitul Golani
2024-02-29 11:52   ` Nautiyal, Ankit K
2024-02-28 14:38 ` [PATCH v12 7/8] drm/i915/display: Compute vrr_vsync params Mitul Golani
2024-02-28 14:38 ` [PATCH v12 8/8] drm/i915/display: Read/Write AS sdp only when sink/source has enabled Mitul Golani
2024-02-28 15:14 ` [PATCH v12 0/8] Enable Adaptive Sync SDP Support for DP Jani Nikula
2024-02-29  4:38   ` Golani, Mitulkumar Ajitkumar
2024-02-29  9:51     ` Jani Nikula
2024-02-28 22:43 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Adaptive Sync SDP Support for DP (rev12) Patchwork
2024-02-28 22:43 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-02-28 22:54 ` ✓ Fi.CI.BAT: success " Patchwork
2024-02-29 17:20 ` ✗ Fi.CI.IGT: failure " Patchwork

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