From: Jani Nikula <jani.nikula@linux.intel.com>
To: John Harrison <john.c.harrison@intel.com>,
Andi Shyti <andi.shyti@linux.intel.com>
Cc: janusz.krzysztofik@intel.com, chris.p.wilson@linux.intel.com,
intel-gfx@lists.freedesktop.org,
Jonathan Cavitt <jonathan.cavitt@intel.com>,
matthew.d.roper@intel.com, nirmoy.das@intel.com
Subject: Re: [Intel-gfx] [PATCH v3 3/4] drm/i915: Perform TLB invalidation on all GTs during suspend/resume
Date: Wed, 04 Oct 2023 10:34:48 +0300 [thread overview]
Message-ID: <87mswyg7s7.fsf@intel.com> (raw)
In-Reply-To: <fabf3fc6-526a-2896-d9b3-1b54f184f82c@intel.com>
On Tue, 03 Oct 2023, John Harrison <john.c.harrison@intel.com> wrote:
> On 10/3/2023 08:59, Andi Shyti wrote:
>> Hi Jani,
>>
>>>> Consider multi-gt support when cancelling all tlb invalidations on
>>>> suspend, and when submitting tlb invalidations on resume.
>>>>
>>>> Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>>>> Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>>> CC: John Harrison <John.C.Harrison@Intel.com>
>>> I guess I'm wondering why the top level suspend hook needs to iterate
>>> gts instead of some lower level thing. We should aim to reduce
>>> gem/gt/display details from the top level.
>> I'm not sure I am understanding the question.
>>
>> The TLB invalidation details are kept under the GT. But when
>> suspend is called, then the GT invalidation has to be triggered
>> by the top levels for each GT. Right?
> I think Jani's point is that the top level should be:
> i915_drm_suspend(...) {
> ...
> intel_tlb_suspend(dev_priv);
> }
>
> Then the TLB suspend helper function calls into the GT / UC layers as
> appropriate. But none of that internal only detail is exposed at the top
> level.
That's right, thanks for clarifying.
BR,
Jani.
>
> John.
>
>>
>> Thanks,
>> Andi
>
--
Jani Nikula, Intel
next prev parent reply other threads:[~2023-10-04 7:34 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-02 17:24 [Intel-gfx] [PATCH v3 1/4] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-02 17:24 ` [Intel-gfx] [PATCH v3 2/4] drm/i915: No TLB invalidation on wedged or suspended GT Jonathan Cavitt
2023-10-03 10:35 ` Tvrtko Ursulin
2023-10-03 11:50 ` Jani Nikula
2023-10-02 17:24 ` [Intel-gfx] [PATCH v3 3/4] drm/i915: Perform TLB invalidation on all GTs during suspend/resume Jonathan Cavitt
2023-10-03 11:48 ` Jani Nikula
2023-10-03 15:59 ` Andi Shyti
2023-10-03 18:52 ` John Harrison
2023-10-04 7:34 ` Jani Nikula [this message]
2023-10-02 17:24 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-02 23:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915: Define and use GuC and CTB TLB invalidation routines Patchwork
2023-10-02 23:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-03 0:01 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-03 10:28 ` [Intel-gfx] [PATCH v3 1/4] " Tvrtko Ursulin
2023-10-03 16:41 ` Andi Shyti
2023-10-03 20:29 ` John Harrison
2023-10-03 21:29 ` Andi Shyti
2023-10-04 7:54 ` Tvrtko Ursulin
2023-10-03 20:23 ` John Harrison
2023-10-04 8:12 ` Tvrtko Ursulin
2023-10-03 11:06 ` Tvrtko Ursulin
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