From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CBC7C433EF for ; Thu, 16 Jun 2022 14:58:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C0B2311A449; Thu, 16 Jun 2022 14:58:07 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 76E1B11A449 for ; Thu, 16 Jun 2022 14:57:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655391443; x=1686927443; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=IHcbLakUxXPtw4lxGA49Cp7l1bsscSZarH8Ycfwotnc=; b=FOPej0c7ZC+b1/p0oVZlleoQ6/J315LP66jVNklN3Hja0R1NA2myuyTw s5MtntPp7Z8aiYDsdyON10bQ0sp7AA4mU+Y0Hu/GV2zYOsBspVK2hQI8F 6x6ciKzK9eceU27ENjh4W4CYWk9nzKsc3luy33KwkucDZdh78DPARKCeT 6SRnTkvPyOUrVsY21n0EmTNRrXZqS5lBRU7CrZRoRxCch1d3/UQJeGspq l5555QNIeDOeFVOEhJLH2RpHki7FzzbUFNyHTex1d4KDYeAq6lu4RwX/z B523egkWHeRSfV82KDrVVJYjtn4Dk7zXlR4YJ35yJivo35+TMQL3k2jZH g==; X-IronPort-AV: E=McAfee;i="6400,9594,10379"; a="278061289" X-IronPort-AV: E=Sophos;i="5.92,305,1650956400"; d="scan'208";a="278061289" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 07:57:23 -0700 X-IronPort-AV: E=Sophos;i="5.92,305,1650956400"; d="scan'208";a="589680169" Received: from aamendol-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.33.35]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2022 07:57:21 -0700 From: Jani Nikula To: priyanka.dandamudi@intel.com, priyanka.dandamudi@intel.com, matthew.auld@intel.com, intel-gfx@lists.freedesktop.org In-Reply-To: <20220616120509.1190329-2-priyanka.dandamudi@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20220616120509.1190329-1-priyanka.dandamudi@intel.com> <20220616120509.1190329-2-priyanka.dandamudi@intel.com> Date: Thu, 16 Jun 2022 17:57:19 +0300 Message-ID: <87mtecvepc.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH i-g-t 1/2] drm/i915: Add support for LMEM PCIe resizable bar X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote: > From: Akeem G Abodunrin > > This patch adds support for the local memory PICe resizable bar, so that Please use imperative. "Add support ..." Please don't refer to "this patch". Please fix your git settings to not prefix with "i-g-t" when sending i915 changes. BR, Jani. > local memory can be resized to the maximum size supported by the device, > and mapped correctly to the PCIe memory bar. It is usual that GPU > devices expose only 256MB BARs primarily to be compatible with 32-bit > systems. So, those devices cannot claim larger memory BAR windows size due > to the system BIOS limitation. With this change, it would be possible to > reprogram the windows of the bridge directly above the requesting device > on the same BAR type. > > Signed-off-by: Akeem G Abodunrin > Signed-off-by: Micha=C5=82 Winiarski > Cc: Stuart Summers > Cc: Michael J Ruhl > Cc: Prathap Kumar Valsan > Signed-off-by: Priyanka Dandamudi > Reviewed-by: Matthew Auld > --- > drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i9= 15_driver.c > index d26dcca7e654..4bdb471cb2e2 100644 > --- a/drivers/gpu/drm/i915/i915_driver.c > +++ b/drivers/gpu/drm/i915/i915_driver.c > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i9= 15) > __intel_gt_reset(to_gt(i915), ALL_ENGINES); > } >=20=20 > +static void __release_bars(struct pci_dev *pdev) > +{ > + int resno; > + > + for (resno =3D PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++= ) { > + if (pci_resource_len(pdev, resno)) > + pci_release_resource(pdev, resno); > + } > +} > + > +static void > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t s= ize) > +{ > + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); > + int bar_size =3D pci_rebar_bytes_to_size(size); > + int ret; > + > + __release_bars(pdev); > + > + ret =3D pci_resize_resource(pdev, resno, bar_size); > + if (ret) { > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n", > + resno, 1 << bar_size, ERR_PTR(ret)); > + return; > + } > + > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); > +} > + > +/* BAR size starts from 1MB - 2^20 */ > +#define BAR_SIZE_SHIFT 20 > +static resource_size_t > +__lmem_rebar_size(struct drm_i915_private *i915, int resno) > +{ > + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); > + u32 rebar =3D pci_rebar_get_possible_sizes(pdev, resno); > + resource_size_t size; > + > + if (!rebar) > + return 0; > + > + size =3D 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT); > + > + if (size <=3D pci_resource_len(pdev, resno)) > + return 0; > + > + return size; > +} > + > +#define LMEM_BAR_NUM 2 > +static void i915_resize_lmem_bar(struct drm_i915_private *i915) > +{ > + struct pci_dev *pdev =3D to_pci_dev(i915->drm.dev); > + struct pci_bus *root =3D pdev->bus; > + struct resource *root_res; > + resource_size_t rebar_size =3D __lmem_rebar_size(i915, LMEM_BAR_NUM); > + u32 pci_cmd; > + int i; > + > + if (!rebar_size) > + return; > + > + /* Find out if root bus contains 64bit memory addressing */ > + while (root->parent) > + root =3D root->parent; > + > + pci_bus_for_each_resource(root, root_res, i) { > + if (root_res && root_res->flags & (IORESOURCE_MEM | > + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull) > + break; > + } > + > + /* pci_resize_resource will fail anyways */ > + if (!root_res) { > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is miss= ing\n"); > + return; > + } > + > + /* First disable PCI memory decoding references */ > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd); > + pci_write_config_dword(pdev, PCI_COMMAND, > + pci_cmd & ~PCI_COMMAND_MEMORY); > + > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size); > + > + pci_assign_unassigned_bus_resources(pdev->bus); > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); > +} > + > /** > * i915_driver_early_probe - setup state not requiring device access > * @dev_priv: device private > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const str= uct pci_device_id *ent) >=20=20 > disable_rpm_wakeref_asserts(&i915->runtime_pm); >=20=20 > + if (HAS_LMEM(i915)) > + i915_resize_lmem_bar(i915); > + > intel_vgpu_detect(i915); >=20=20 > ret =3D intel_gt_probe_all(i915); --=20 Jani Nikula, Intel Open Source Graphics Center