From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FE1FC43334 for ; Thu, 2 Jun 2022 09:43:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6DD510E85F; Thu, 2 Jun 2022 09:43:43 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id A385F10E85F for ; Thu, 2 Jun 2022 09:43:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654163021; x=1685699021; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=pJCTdYbAVaZI5YNUcsmJPOe1AA44aG8wLW5OibOlEg8=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Parse max link rate from the eDP BDB block X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, 01 Jun 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > The eDP BDB block has gained yet another max link rate field. > Let's parse it and consult it during the source rate filtering. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 > --- > drivers/gpu/drm/i915/display/intel_bios.c | 4 ++++ > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 23 +++++++++++++++++-- > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 + > 4 files changed, 27 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/= i915/display/intel_bios.c > index d701854dc429..b35afd39413d 100644 > --- a/drivers/gpu/drm/i915/display/intel_bios.c > +++ b/drivers/gpu/drm/i915/display/intel_bios.c > @@ -1461,6 +1461,10 @@ parse_edp(struct drm_i915_private *i915, >=20=20 > panel->vbt.edp.drrs_msa_timing_delay =3D > (edp->sdrrs_msa_timing_delay >> (panel_type * 2)) & 3; > + > + if (i915->vbt.version >=3D 244) > + panel->vbt.edp.max_link_rate =3D > + edp->edp_max_port_link_rate[panel_type] * 2; > } >=20=20 > static void > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers= /gpu/drm/i915/display/intel_display_types.h > index 9b44358e8d9e..8b0949b6dc75 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -300,6 +300,7 @@ struct intel_vbt_panel_data { > enum drrs_type drrs_type; >=20=20 > struct { > + int max_link_rate; > int rate; > int lanes; > int preemphasis; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i9= 15/display/intel_dp.c > index 03af93ef9e93..2b84d6fcba4a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -408,6 +408,26 @@ static int ehl_max_source_rate(struct intel_dp *inte= l_dp) > return 810000; > } >=20=20 > +static int vbt_max_link_rate(struct intel_dp *intel_dp) > +{ > + struct intel_encoder *encoder =3D &dp_to_dig_port(intel_dp)->base; > + struct intel_connector *connector =3D intel_dp->attached_connector; > + int max_rate; > + > + max_rate =3D intel_bios_dp_max_link_rate(encoder); > + > + if (intel_dp_is_edp(intel_dp)) { > + int edp_max_rate =3D connector->panel.vbt.edp.max_link_rate; > + > + if (max_rate && edp_max_rate) > + max_rate =3D min(max_rate, edp_max_rate); I think the spec is a bit unambigous about the relationship of these two, but this seems sane. *shrug* Reviewed-by: Jani Nikula > + else if (edp_max_rate) > + max_rate =3D edp_max_rate; > + } > + > + return max_rate; > +} > + > static void > intel_dp_set_source_rates(struct intel_dp *intel_dp) > { > @@ -429,7 +449,6 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) > 162000, 270000 > }; > struct intel_digital_port *dig_port =3D dp_to_dig_port(intel_dp); > - struct intel_encoder *encoder =3D &dig_port->base; > struct drm_i915_private *dev_priv =3D to_i915(dig_port->base.base.dev); > const int *source_rates; > int size, max_rate =3D 0, vbt_max_rate; > @@ -465,7 +484,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) > size =3D ARRAY_SIZE(g4x_rates); > } >=20=20 > - vbt_max_rate =3D intel_bios_dp_max_link_rate(encoder); > + vbt_max_rate =3D vbt_max_link_rate(intel_dp); > if (max_rate && vbt_max_rate) > max_rate =3D min(max_rate, vbt_max_rate); > else if (vbt_max_rate) > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/= drm/i915/display/intel_vbt_defs.h > index 58aee0a040cf..f8e5097222f2 100644 > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h > @@ -697,6 +697,7 @@ struct bdb_edp { > u16 apical_enable; /* 203 */ > struct edp_apical_params apical_params[16]; /* 203 */ > u16 edp_fast_link_training_rate[16]; /* 224 */ > + u16 edp_max_port_link_rate[16]; /* 244 */ > } __packed; >=20=20 > /* --=20 Jani Nikula, Intel Open Source Graphics Center