diff for duplicates of <87mtmdcrf2.fsf@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index 1dfbc23..43fa707 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -23,25 +23,25 @@ Machnikowski, Maciej <maciej.machnikowski@intel.com> writes: >> > +input frequency - either on the PHY CLK input, or on a dedicated >> > +TX clock input. >> > + ->> > + ???????????????????????? ->> > + ? RX ? TX ? ->> > + 1 ? lanes ? lanes ? 1 ->> > + ???????????? ? ??????? ->> > + 2 ? ? ? ? 2 ->> > + ???????? ? ? ??????? ->> > + 3 ? ? ? ? ? 3 ->> > + ???????? ? ? ??????? ->> > + ? ?????? ? ? ->> > + ? \____/ ? ? ->> > + ???????????????????????? ->> > + 1? 2? ? ->> > + RCLK out? ? ? TX CLK in ->> > + ? ? ? ->> > + ??????????????????? ->> > + ? ? ->> > + ? EEC ? ->> > + ? ? ->> > + ??????????????????? +>> > + ┌───────────┬──────────┐ +>> > + │ RX │ TX │ +>> > + 1 │ lanes │ lanes │ 1 +>> > + ───►├──────┐ │ ├─────► +>> > + 2 │ │ │ │ 2 +>> > + ───►├──┐ │ │ ├─────► +>> > + 3 │ │ │ │ │ 3 +>> > + ───►├─▼▼ ▼ │ ├─────► +>> > + │ ────── │ │ +>> > + │ \____/ │ │ +>> > + └──┼──┼─────┴──────────┘ +>> > + 1│ 2│ ▲ +>> > + RCLK out│ │ │ TX CLK in +>> > + ▼ ▼ │ +>> > + ┌─────────────┴───┐ +>> > + │ │ +>> > + │ EEC │ +>> > + │ │ +>> > + └─────────────────┘ >> > + >> > +The EEC can synchronize its frequency to one of the synchronization >> inputs @@ -221,7 +221,7 @@ a time when it is superseded by a better interface. >> pins, not present this information as if they own it. A first-class EEC >> would also allow to later figure out how to hook up PHC and EEC. > -> We have the userspace tool, but can?t upstream it until we define +> We have the userspace tool, but can’t upstream it until we define > kernel Interfaces. It's paragraph 22 :( I'm sure you do, presumably you test this somehow. Still, as a potential diff --git a/a/content_digest b/N1/content_digest index 92465dc..3e67d2f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,9 +3,24 @@ "ref\087r1bqcyto.fsf@nvidia.com\0" "ref\0MW5PR11MB5812B0A4E6227C6896AC12B5EA929@MW5PR11MB5812.namprd11.prod.outlook.com\0" "From\0Petr Machata <petrm@nvidia.com>\0" - "Subject\0[Intel-wired-lan] [PATCH v2 net-next 6/6] docs: net: Add description of SyncE interfaces\0" + "Subject\0Re: [PATCH v2 net-next 6/6] docs: net: Add description of SyncE interfaces\0" "Date\0Tue, 9 Nov 2021 15:52:33 +0100\0" - "To\0intel-wired-lan@osuosl.org\0" + "To\0Machnikowski" + " Maciej <maciej.machnikowski@intel.com>\0" + "Cc\0Petr Machata <petrm@nvidia.com>" + netdev@vger.kernel.org <netdev@vger.kernel.org> + intel-wired-lan@lists.osuosl.org <intel-wired-lan@lists.osuosl.org> + richardcochran@gmail.com <richardcochran@gmail.com> + abyagowi@fb.com <abyagowi@fb.com> + Nguyen + Anthony L <anthony.l.nguyen@intel.com> + davem@davemloft.net <davem@davemloft.net> + kuba@kernel.org <kuba@kernel.org> + linux-kselftest@vger.kernel.org <linux-kselftest@vger.kernel.org> + idosch@idosch.org <idosch@idosch.org> + mkubecek@suse.cz <mkubecek@suse.cz> + saeed@kernel.org <saeed@kernel.org> + " michael.chan@broadcom.com <michael.chan@broadcom.com>\0" "\00:1\0" "b\0" "\n" @@ -33,25 +48,25 @@ ">> > +input frequency - either on the PHY CLK input, or on a dedicated\n" ">> > +TX clock input.\n" ">> > +\n" - ">> > + ????????????????????????\n" - ">> > + ? RX ? TX ?\n" - ">> > + 1 ? lanes ? lanes ? 1\n" - ">> > + ???????????? ? ???????\n" - ">> > + 2 ? ? ? ? 2\n" - ">> > + ???????? ? ? ???????\n" - ">> > + 3 ? ? ? ? ? 3\n" - ">> > + ???????? ? ? ???????\n" - ">> > + ? ?????? ? ?\n" - ">> > + ? \\____/ ? ?\n" - ">> > + ????????????????????????\n" - ">> > + 1? 2? ?\n" - ">> > + RCLK out? ? ? TX CLK in\n" - ">> > + ? ? ?\n" - ">> > + ???????????????????\n" - ">> > + ? ?\n" - ">> > + ? EEC ?\n" - ">> > + ? ?\n" - ">> > + ???????????????????\n" + ">> > + \342\224\214\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\254\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\220\n" + ">> > + \342\224\202 RX \342\224\202 TX \342\224\202\n" + ">> > + 1 \342\224\202 lanes \342\224\202 lanes \342\224\202 1\n" + ">> > + \342\224\200\342\224\200\342\224\200\342\226\272\342\224\234\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\220 \342\224\202 \342\224\234\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\226\272\n" + ">> > + 2 \342\224\202 \342\224\202 \342\224\202 \342\224\202 2\n" + ">> > + \342\224\200\342\224\200\342\224\200\342\226\272\342\224\234\342\224\200\342\224\200\342\224\220 \342\224\202 \342\224\202 \342\224\234\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\226\272\n" + ">> > + 3 \342\224\202 \342\224\202 \342\224\202 \342\224\202 \342\224\202 3\n" + ">> > + \342\224\200\342\224\200\342\224\200\342\226\272\342\224\234\342\224\200\342\226\274\342\226\274 \342\226\274 \342\224\202 \342\224\234\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\226\272\n" + ">> > + \342\224\202 \342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200 \342\224\202 \342\224\202\n" + ">> > + \342\224\202 \\____/ \342\224\202 \342\224\202\n" + ">> > + \342\224\224\342\224\200\342\224\200\342\224\274\342\224\200\342\224\200\342\224\274\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\264\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\230\n" + ">> > + 1\342\224\202 2\342\224\202 \342\226\262\n" + ">> > + RCLK out\342\224\202 \342\224\202 \342\224\202 TX CLK in\n" + ">> > + \342\226\274 \342\226\274 \342\224\202\n" + ">> > + \342\224\214\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\264\342\224\200\342\224\200\342\224\200\342\224\220\n" + ">> > + \342\224\202 \342\224\202\n" + ">> > + \342\224\202 EEC \342\224\202\n" + ">> > + \342\224\202 \342\224\202\n" + ">> > + \342\224\224\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\200\342\224\230\n" ">> > +\n" ">> > +The EEC can synchronize its frequency to one of the synchronization\n" ">> inputs\n" @@ -231,7 +246,7 @@ ">> pins, not present this information as if they own it. A first-class EEC\n" ">> would also allow to later figure out how to hook up PHC and EEC.\n" ">\n" - "> We have the userspace tool, but can?t upstream it until we define\n" + "> We have the userspace tool, but can\342\200\231t upstream it until we define\n" "> kernel Interfaces. It's paragraph 22 :(\n" "\n" "I'm sure you do, presumably you test this somehow. Still, as a potential\n" @@ -244,4 +259,4 @@ "stuff. I doubt anybody actually looks at that code, ain't nobody got\n" time for that, but really there's no catch 22. -35d763882d844f372df3a9cf4ef17c1a88c7c41758b1951f32d6cfe4b45e8b22 +7f712fdeb146fbdf462549b0e3fe9fea3f7649ca33381d9fe750db1304ce4a98
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