From: Jani Nikula <jani.nikula@linux.intel.com>
To: Tvrtko Ursulin <tursulin@ursulin.net>, Intel-gfx@lists.freedesktop.org
Subject: Re: [RFC 11/15] drm/i915: Use INTEL_GEN everywhere
Date: Fri, 09 Feb 2018 12:14:10 +0200 [thread overview]
Message-ID: <87mv0i8o7h.fsf@intel.com> (raw)
In-Reply-To: <20180208130606.15556-12-tvrtko.ursulin@linux.intel.com>
On Thu, 08 Feb 2018, Tvrtko Ursulin <tursulin@ursulin.net> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Coccinelle patch:
>
> @@
> identifier p;
> @@
> -INTEL_INFO(p)->gen
> +INTEL_GEN(p)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
I think you should get this merged outside of this series. Please rename
->gen to ->__gen or something to discourage its direct use while at it.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +-
> drivers/gpu/drm/i915/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_panel.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++----
> drivers/gpu/drm/i915/intel_psr.c | 4 ++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
> 16 files changed, 29 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c1b80cd52f9e..1d5208f24b60 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5420,10 +5420,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
> {
> int i;
>
> - if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
> + if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) &&
> !IS_CHERRYVIEW(dev_priv))
> dev_priv->num_fence_regs = 32;
> - else if (INTEL_INFO(dev_priv)->gen >= 4 ||
> + else if (INTEL_GEN(dev_priv) >= 4 ||
> IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
> IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
> dev_priv->num_fence_regs = 16;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 955ce7bee448..0c0f1affddad 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2109,7 +2109,7 @@ static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
> ppgtt->base.i915 = dev_priv;
> ppgtt->base.dma = &dev_priv->drm.pdev->dev;
>
> - if (INTEL_INFO(dev_priv)->gen < 8)
> + if (INTEL_GEN(dev_priv) < 8)
> return gen6_ppgtt_init(ppgtt);
> else
> return gen8_ppgtt_init(ppgtt);
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index d3f222fa6356..f18da9e2be8e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -356,7 +356,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
> reserved_base = 0;
> reserved_size = 0;
>
> - switch (INTEL_INFO(dev_priv)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 2:
> case 3:
> break;
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 522d54fecb53..ff455c724775 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -704,7 +704,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> - } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
> + } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
> dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
> dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 4e74aa2f16bc..aa4df6548771 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -391,7 +391,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
> static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
> bool alternate)
> {
> - switch (INTEL_INFO(dev_priv)->gen) {
> + switch (INTEL_GEN(dev_priv)) {
> case 2:
> return alternate ? 66667 : 48000;
> case 3:
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..aab6d1538fff 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2233,7 +2233,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> return max_cdclk_freq;
> else if (IS_CHERRYVIEW(dev_priv))
> return max_cdclk_freq*95/100;
> - else if (INTEL_INFO(dev_priv)->gen < 4)
> + else if (INTEL_GEN(dev_priv) < 4)
> return 2*max_cdclk_freq*90/100;
> else
> return max_cdclk_freq*90/100;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cfcd9cb37d5d..8ca376aca8bd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2152,7 +2152,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>
> I915_WRITE(DPLL_CTRL2, val);
>
> - } else if (INTEL_INFO(dev_priv)->gen < 9) {
> + } else if (INTEL_GEN(dev_priv) < 9) {
> I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 60ba5bb3f34c..0d5207dbfdac 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2029,12 +2029,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr
>
> static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return 256 * 1024;
> else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
> IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return 128 * 1024;
> - else if (INTEL_INFO(dev_priv)->gen >= 4)
> + else if (INTEL_GEN(dev_priv) >= 4)
> return 4 * 1024;
> else
> return 0;
> @@ -6307,7 +6307,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
> const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /* GDG double wide on either pipe, otherwise pipe A only */
> - return INTEL_INFO(dev_priv)->gen < 4 &&
> + return INTEL_GEN(dev_priv) < 4 &&
> (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
> }
>
> @@ -8194,7 +8194,7 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_crtc_state *config = intel_crtc->config;
>
> - if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
> + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
> u32 val = 0;
>
> switch (intel_crtc->config->pipe_bpp) {
> @@ -13947,7 +13947,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> * gen2/3 display engine uses the fence if present,
> * so the tiling mode must match the fb modifier exactly.
> */
> - if (INTEL_INFO(dev_priv)->gen < 4 &&
> + if (INTEL_GEN(dev_priv) < 4 &&
> tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
> DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
> goto err;
> @@ -14162,7 +14162,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> {
> intel_init_cdclk_hooks(dev_priv);
>
> - if (INTEL_INFO(dev_priv)->gen >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> dev_priv->display.get_pipe_config = haswell_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> skylake_get_initial_plane_config;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f10a14330e7c..abbe1e4e0af5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1467,7 +1467,7 @@ static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
> static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return skl_aux_ctl_reg(dev_priv, port);
> else if (HAS_PCH_SPLIT(dev_priv))
> return ilk_aux_ctl_reg(dev_priv, port);
> @@ -1478,7 +1478,7 @@ static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
> static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
> enum port port, int index)
> {
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return skl_aux_data_reg(dev_priv, port, index);
> else if (HAS_PCH_SPLIT(dev_priv))
> return ilk_aux_data_reg(dev_priv, port, index);
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index ef80499113ee..4677ac0b10d7 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -189,7 +189,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
> /* Convert from 100ms to 100us units */
> pps->t4 = val * 1000;
>
> - if (INTEL_INFO(dev_priv)->gen <= 4 &&
> + if (INTEL_GEN(dev_priv) <= 4 &&
> pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
> DRM_DEBUG_KMS("Panel power timings uninitialized, "
> "setting defaults\n");
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index f4c46b0b8f0a..abb7a8c1e340 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -187,7 +187,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> table->table = broxton_mocs_table;
> result = true;
> } else {
> - WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
> + WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
> "Platform that should have a MOCS table does not.\n");
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index e702a6487aa9..78a53c8b1789 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -497,7 +497,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector)
> u32 val;
>
> val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
> - if (INTEL_INFO(dev_priv)->gen < 4)
> + if (INTEL_GEN(dev_priv) < 4)
> val >>= 1;
>
> if (panel->backlight.combination_mode) {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 063c885175e7..7a112d075c24 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6940,7 +6940,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> * No floor required for ring frequency on SKL.
> */
> ring_freq = gpu_freq;
> - } else if (INTEL_INFO(dev_priv)->gen >= 8) {
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> /* max(2 * GT, DDR). NB: GT is 50MHz units */
> ring_freq = max(min_ring_freq, gpu_freq);
> } else if (IS_HASWELL(dev_priv)) {
> @@ -7551,7 +7551,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
> {
> unsigned long val;
>
> - if (INTEL_INFO(dev_priv)->gen != 5)
> + if (INTEL_GEN(dev_priv) != 5)
> return 0;
>
> spin_lock_irq(&mchdev_lock);
> @@ -7635,7 +7635,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
>
> void i915_update_gfx_val(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev_priv)->gen != 5)
> + if (INTEL_GEN(dev_priv) != 5)
> return;
>
> spin_lock_irq(&mchdev_lock);
> @@ -7686,7 +7686,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
> {
> unsigned long val;
>
> - if (INTEL_INFO(dev_priv)->gen != 5)
> + if (INTEL_GEN(dev_priv) != 5)
> return 0;
>
> spin_lock_irq(&mchdev_lock);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index e9feffdea899..2ef374f936b9 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -126,7 +126,7 @@ static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
> static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return DP_AUX_CH_CTL(port);
> else
> return EDP_PSR_AUX_CTL;
> @@ -135,7 +135,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
> static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
> enum port port, int index)
> {
> - if (INTEL_INFO(dev_priv)->gen >= 9)
> + if (INTEL_GEN(dev_priv) >= 9)
> return DP_AUX_CH_DATA(port, index);
> else
> return EDP_PSR_AUX_DATA(index);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f93e4532371a..c91d7106fbcf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -655,7 +655,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> if (IS_GEN(dev_priv, 6, 7))
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> - if (INTEL_INFO(dev_priv)->gen >= 6)
> + if (INTEL_GEN(dev_priv) >= 6)
> I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
>
> return init_workarounds_ring(engine);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 164dbb8cfa36..73959ae56241 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1874,9 +1874,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
> if (!i915_modparams.reset)
> return NULL;
>
> - if (INTEL_INFO(dev_priv)->gen >= 8)
> + if (INTEL_GEN(dev_priv) >= 8)
> return gen8_reset_engines;
> - else if (INTEL_INFO(dev_priv)->gen >= 6)
> + else if (INTEL_GEN(dev_priv) >= 6)
> return gen6_reset_engines;
> else if (IS_GEN5(dev_priv))
> return ironlake_do_reset;
> @@ -1884,7 +1884,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
> return g4x_do_reset;
> else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
> return g33_do_reset;
> - else if (INTEL_INFO(dev_priv)->gen >= 3)
> + else if (INTEL_GEN(dev_priv) >= 3)
> return i915_do_reset;
> else
> return NULL;
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-02-09 10:14 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-08 13:05 [RFC 00/15] Selectable platform support Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 01/15] drm/i915: Make I830 platform support optional Tvrtko Ursulin
2018-02-08 13:23 ` Chris Wilson
2018-02-09 11:26 ` Jani Nikula
2018-02-08 13:05 ` [RFC 02/15] drm/i915: Make I845G " Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 03/15] drm/i915: Make I85X " Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 04/15] drm/i915: Make I865G " Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 05/15] drm/i915: Make GEN2 " Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 06/15] drm/i915: Make Gen3 platforms " Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 07/15] drm/i915: Make Gen4 " Tvrtko Ursulin
2018-02-08 13:05 ` [RFC 08/15] drm/i915: Make Ironlake/Gen5 " Tvrtko Ursulin
2018-02-08 13:06 ` [RFC 09/15] drm/i915: Make Sandybridge/Gen6 " Tvrtko Ursulin
2018-02-08 13:06 ` [RFC 10/15] drm/i915: Make Gen7/7.5 platform " Tvrtko Ursulin
2018-02-08 13:06 ` [RFC 11/15] drm/i915: Use INTEL_GEN everywhere Tvrtko Ursulin
2018-02-09 10:14 ` Jani Nikula [this message]
2018-02-09 21:59 ` [PATCH] __gen__ Chris Wilson
2018-02-09 10:20 ` [RFC 11/15] drm/i915: Use INTEL_GEN everywhere Chris Wilson
2018-02-08 13:06 ` [RFC 12/15] drm/i915: Favour IS_GENx Tvrtko Ursulin
2018-02-08 13:06 ` [RFC 13/15] drm/i915: IS_GEN range helpers Tvrtko Ursulin
2018-02-08 13:06 ` [RFC 14/15] drm/i915: Use new " Tvrtko Ursulin
2018-02-08 14:22 ` Ville Syrjälä
2018-02-08 14:34 ` Tvrtko Ursulin
2018-02-08 14:46 ` Chris Wilson
2018-02-08 15:13 ` Mika Kuoppala
2018-02-08 15:53 ` Ville Syrjälä
2018-02-09 11:18 ` Jani Nikula
2018-02-09 14:48 ` Ville Syrjälä
2018-02-09 15:01 ` Chris Wilson
2018-02-09 15:12 ` Ville Syrjälä
2018-02-10 22:51 ` Chris Wilson
2018-02-08 13:06 ` [RFC 15/15] drm/i915: Replace some negative Gen checks Tvrtko Ursulin
2018-02-09 10:18 ` Jani Nikula
2018-02-09 10:19 ` Chris Wilson
2018-02-08 13:26 ` [RFC 00/15] Selectable platform support Chris Wilson
2018-02-08 14:06 ` Tvrtko Ursulin
2018-02-08 15:07 ` Joonas Lahtinen
2018-02-09 11:49 ` Jani Nikula
2018-02-09 12:02 ` Chris Wilson
2018-02-08 15:28 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-02-09 10:48 ` [RFC 00/15] " Tvrtko Ursulin
2018-02-09 10:50 ` Chris Wilson
2018-02-09 11:01 ` Tvrtko Ursulin
2018-02-09 11:19 ` Chris Wilson
2018-02-09 21:14 ` Chris Wilson
2018-02-09 11:32 ` Jani Nikula
2018-02-09 22:23 ` ✗ Fi.CI.BAT: failure for Selectable platform support (rev2) Patchwork
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