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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/i915/cmdparser: Limit clflush to active cachelines
Date: Fri, 10 Mar 2017 14:41:16 +0200	[thread overview]
Message-ID: <87mvct2tjn.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20170310115518.13832-1-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> We only need to clflush those cachelines that we have validated to be
> read by the GPU. Userspace typically fills the batch length in
> correctly, the exceptions tend to be explicit tests within igt.
>
> v2: Use ptr_mask_bits() to make Mika happy
> v3: cmd is not advanced on MI_BBE, so make sure to include an extra
> dword in the clflush.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

I am now very happy.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 21b1cd917d81..7af100f84410 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1279,11 +1279,17 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
>  	 * space. Parsing should be faster in some cases this way.
>  	 */
>  	batch_end = cmd + (batch_len / sizeof(*batch_end));
> -	while (cmd < batch_end) {
> +	do {
>  		u32 length;
>  
> -		if (*cmd == MI_BATCH_BUFFER_END)
> +		if (*cmd == MI_BATCH_BUFFER_END) {
> +			if (needs_clflush_after) {
> +				void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);
> +				drm_clflush_virt_range(ptr,
> +						       (void *)(cmd + 1) - ptr);
> +			}
>  			break;
> +		}
>  
>  		desc = find_cmd(engine, *cmd, desc, &default_desc);
>  		if (!desc) {
> @@ -1323,17 +1329,14 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
>  		}
>  
>  		cmd += length;
> -	}
> -
> -	if (cmd >= batch_end) {
> -		DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
> -		ret = -EINVAL;
> -	}
> +		if  (cmd >= batch_end) {
> +			DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
> +			ret = -EINVAL;
> +			break;
> +		}
> +	} while (1);
>  
> -	if (ret == 0 && needs_clflush_after)
> -		drm_clflush_virt_range(shadow_batch_obj->mm.mapping, batch_len);
>  	i915_gem_object_unpin_map(shadow_batch_obj);
> -
>  	return ret;
>  }
>  
> -- 
> 2.11.0
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  reply	other threads:[~2017-03-10 12:41 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-10  9:42 [PATCH] drm/i915/cmdparser: Limit clflush to active cachelines Chris Wilson
2017-03-10  9:58 ` Mika Kuoppala
2017-03-10 10:04   ` Chris Wilson
2017-03-10 10:19     ` Chris Wilson
2017-03-10 10:26       ` Mika Kuoppala
2017-03-10 10:39         ` Chris Wilson
2017-03-10 10:42           ` Mika Kuoppala
2017-03-10 10:50             ` Chris Wilson
2017-03-10 10:46 ` [PATCH v2] " Chris Wilson
2017-03-10 11:19   ` Mika Kuoppala
2017-03-10 11:39     ` Chris Wilson
2017-03-10 11:55 ` [PATCH v3] " Chris Wilson
2017-03-10 12:41   ` Mika Kuoppala [this message]
2017-03-10 13:19     ` Chris Wilson

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