From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH] drm/i915: disable non-sequential pfits on ivb/hsw Date: Thu, 14 Jan 2016 10:23:13 +0200 Message-ID: <87mvs8y3gu.fsf@intel.com> References: <20160113143347.GA4866@localhost> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id BA98B720D6 for ; Thu, 14 Jan 2016 00:23:15 -0800 (PST) In-Reply-To: <20160113143347.GA4866@localhost> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Bainbridge , daniel.vetter@intel.com Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gV2VkLCAxMyBKYW4gMjAxNiwgQ2hyaXMgQmFpbmJyaWRnZSA8Y2hyaXMuYmFpbmJyaWRnZUBn bWFpbC5jb20+IHdyb3RlOgo+IFRoZSBleGlzdGluZyBjb2RlIGFzc3VtZXMgYSBzZXF1ZW50aWFs IG1hcHBpbmcgb2YgcGFuZWwgZml0dGVycyB0byBwaXBlcwo+IChwZml0MC1waXBlQSwgcGZpdDEt cGlwZUIsIHBmaXQyLXBpcGVDKSwgYnV0IGJvb3QgZmlybXdhcmUgY2FuCj4gYXJiaXRyYXJpbHkg YXNzaWduIGFueSBwaXBlIHRvIGEgcGZpdCBvbiBJVkIgaGFyZHdhcmUgZS5nLiBNYWNib29rIFVF RkkKPiB1c2VzIHBmaXQgMCBhbmQgcGlwZSBDIGZvciBlRFAxIHdoZW4gdGhlIGZpcm13YXJlIGJv b3RzIGluIGEgbm9uLTE2OjEwCj4gcmVzb2x1dGlvbiAodGhlIGxhc3QtdXNlZCByZXNvbHV0aW9u IGlzIHN0b3JlZCBpbiBOVlJBTSBieSBPUyBYIHNvIHRoZQo+IGZpcm13YXJlIGNhbiBpbW1lZGlh dGVseSByZXN0b3JlIGl0IGF0IGJvb3QpLiBXaGVuIHRoaXMgaGFwcGVucywgdGhlCj4gZGlzcGxh eSB3aWxsIGFwcGVhciBsZXR0ZXJib3hlZCBkdWUgdG8gaW5jb3JyZWN0IGFzcGVjdCByYXRpbyBh bmQKPiBhdHRlbXB0aW5nIHRvIHN3aXRjaCB0byBhbHRlcm5hdGl2ZSByZXNvbHV0aW9ucyB3aWxs IGZhaWwuIEZpeCB0aGlzIGJ5Cj4gZGlzYWJsaW5nIGFueSBwYW5lbCBmaXR0ZXJzIHdoaWNoIGhh dmUgYmVlbiBub24tc2VxdWVudGlhbGx5IGFzc2lnbmVkIGF0Cj4gYm9vdCB0aW1lLgo+Cj4gTGlu azogaHR0cHM6Ly9idWdzLmZyZWVkZXNrdG9wLm9yZy9zaG93X2J1Zy5jZ2k/aWQ9OTM1MjMKCnMv TGluay9CdWd6aWxsYS8KCj4gU2lnbmVkLW9mZi1ieTogQ2hyaXMgQmFpbmJyaWRnZSA8Y2hyaXMu YmFpbmJyaWRnZUBnbWFpbC5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVs X2Rpc3BsYXkuYyB8IDI2ICsrKysrKysrKysrKysrKysrKy0tLS0tLS0tCj4gIDEgZmlsZSBjaGFu Z2VkLCAxOCBpbnNlcnRpb25zKCspLCA4IGRlbGV0aW9ucygtKQo+Cj4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX2Rpc3BsYXkuYwo+IGluZGV4IDMyY2Y5NzM0Njk3OC4uOWU1ODgxMzlhMmRkIDEwMDY0 NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwo+ICsrKyBiL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwo+IEBAIC05MTcwLDYgKzkxNzAsMjQg QEAgc3RhdGljIHZvaWQgaXJvbmxha2VfZ2V0X3BmaXRfY29uZmlnKHN0cnVjdCBpbnRlbF9jcnRj ICpjcnRjLAo+ICAJc3RydWN0IGRybV9kZXZpY2UgKmRldiA9IGNydGMtPmJhc2UuZGV2Owo+ICAJ c3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gZGV2LT5kZXZfcHJpdmF0ZTsKPiAg CXVpbnQzMl90IHRtcDsKPiArCWludCBwaXBlOwo+ICsKPiArCS8qCj4gKwkgKiBQRl9DVEwgYXNz dW1lcyBwYW5lbCBmaXR0ZXIgMCBpcyBvbiBwaXBlIEEsIHBhbmVsIGZpdHRlciAxIGlzIG9uCj4g KwkgKiBwaXBlIEIsIGFuZCBwYW5lbCBmaXR0ZXIgMiBpcyBvbiBwaXBlIEMsIGJ1dCBmaXJtd2Fy ZSBjYW4gaW5pdCBJVkIKPiArCSAqIHBhbmVsIGZpdHRlcnMgdG8gYW55IGFyYml0cmFyeSBwaXBl IChNYWNib29rIFVFRkkgdXNlcyBwZml0IDAgZm9yCj4gKwkgKiBwaXBlIEMpLCBzbyBmaW5kIGFu ZCBkaXNhYmxlIGFueSBvdGhlciBtYXBwaW5ncy4KPiArCSAqLwo+ICsJZm9yIChwaXBlID0gMDsg cGlwZSA8IElOVEVMX0lORk8oZGV2KS0+bnVtX3BpcGVzOyBwaXBlKyspIHsKPiArCQl0bXAgPSBJ OTE1X1JFQUQoUEZfQ1RMKHBpcGUpKTsKPiArCQlpZiAoSVNfR0VONyhkZXYpICYmICh0bXAgJiBQ Rl9FTkFCTEUpICYmCj4gKwkJICAgIFBGX1BJUEVfU0VMX0lWQihwaXBlKSAhPSAodG1wICYgUEZf UElQRV9TRUxfTUFTS19JVkIpKSB7Cj4gKwkJCURSTV9ERUJVR19LTVMoImRpc2FibGluZyBpbml0 aWFsIHBhbmVsIGZpdHRlclxuIik7Cj4gKwkJCUk5MTVfV1JJVEUoUEZfQ1RMKHBpcGUpLCAwKTsK PiArCQkJSTkxNV9XUklURShQRl9XSU5fUE9TKHBpcGUpLCAwKTsKPiArCQkJSTkxNV9XUklURShQ Rl9XSU5fU1oocGlwZSksIDApOwo+ICsJCX0KPiArCX0KPiAgCj4gIAl0bXAgPSBJOTE1X1JFQUQo UEZfQ1RMKGNydGMtPnBpcGUpKTsKPiAgCj4gQEAgLTkxNzcsMTQgKzkxOTUsNiBAQCBzdGF0aWMg dm9pZCBpcm9ubGFrZV9nZXRfcGZpdF9jb25maWcoc3RydWN0IGludGVsX2NydGMgKmNydGMsCj4g IAkJcGlwZV9jb25maWctPnBjaF9wZml0LmVuYWJsZWQgPSB0cnVlOwo+ICAJCXBpcGVfY29uZmln LT5wY2hfcGZpdC5wb3MgPSBJOTE1X1JFQUQoUEZfV0lOX1BPUyhjcnRjLT5waXBlKSk7Cj4gIAkJ cGlwZV9jb25maWctPnBjaF9wZml0LnNpemUgPSBJOTE1X1JFQUQoUEZfV0lOX1NaKGNydGMtPnBp cGUpKTsKPiAtCj4gLQkJLyogV2UgY3VycmVudGx5IGRvIG5vdCBmcmVlIGFzc2lnbmVtZW50cyBv ZiBwYW5lbCBmaXR0ZXJzIG9uCj4gLQkJICogaXZiL2hzdyAoc2luY2Ugd2UgZG9uJ3QgdXNlIHRo ZSBoaWdoZXIgdXBzY2FsaW5nIG1vZGVzIHdoaWNoCj4gLQkJICogZGlmZmVyZW50aWF0ZXMgdGhl bSkgc28ganVzdCBXQVJOIGFib3V0IHRoaXMgY2FzZSBmb3Igbm93LiAqLwo+IC0JCWlmIChJU19H RU43KGRldikpIHsKPiAtCQkJV0FSTl9PTigodG1wICYgUEZfUElQRV9TRUxfTUFTS19JVkIpICE9 Cj4gLQkJCQlQRl9QSVBFX1NFTF9JVkIoY3J0Yy0+cGlwZSkpOwo+IC0JCX0KPiAgCX0KPiAgfQoK LS0gCkphbmkgTmlrdWxhLCBJbnRlbCBPcGVuIFNvdXJjZSBUZWNobm9sb2d5IENlbnRlcgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFp bGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZy ZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751180AbcANIXR (ORCPT ); Thu, 14 Jan 2016 03:23:17 -0500 Received: from mga02.intel.com ([134.134.136.20]:55877 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750811AbcANIXQ (ORCPT ); Thu, 14 Jan 2016 03:23:16 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,293,1449561600"; d="scan'208";a="892950664" From: Jani Nikula To: Chris Bainbridge , daniel.vetter@intel.com Cc: intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH] drm/i915: disable non-sequential pfits on ivb/hsw In-Reply-To: <20160113143347.GA4866@localhost> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20160113143347.GA4866@localhost> User-Agent: Notmuch/0.21+34~g7dd0d52 (http://notmuchmail.org) Emacs/24.4.1 (x86_64-pc-linux-gnu) Date: Thu, 14 Jan 2016 10:23:13 +0200 Message-ID: <87mvs8y3gu.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 13 Jan 2016, Chris Bainbridge wrote: > The existing code assumes a sequential mapping of panel fitters to pipes > (pfit0-pipeA, pfit1-pipeB, pfit2-pipeC), but boot firmware can > arbitrarily assign any pipe to a pfit on IVB hardware e.g. Macbook UEFI > uses pfit 0 and pipe C for eDP1 when the firmware boots in a non-16:10 > resolution (the last-used resolution is stored in NVRAM by OS X so the > firmware can immediately restore it at boot). When this happens, the > display will appear letterboxed due to incorrect aspect ratio and > attempting to switch to alternative resolutions will fail. Fix this by > disabling any panel fitters which have been non-sequentially assigned at > boot time. > > Link: https://bugs.freedesktop.org/show_bug.cgi?id=93523 s/Link/Bugzilla/ > Signed-off-by: Chris Bainbridge > --- > drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++-------- > 1 file changed, 18 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 32cf97346978..9e588139a2dd 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9170,6 +9170,24 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t tmp; > + int pipe; > + > + /* > + * PF_CTL assumes panel fitter 0 is on pipe A, panel fitter 1 is on > + * pipe B, and panel fitter 2 is on pipe C, but firmware can init IVB > + * panel fitters to any arbitrary pipe (Macbook UEFI uses pfit 0 for > + * pipe C), so find and disable any other mappings. > + */ > + for (pipe = 0; pipe < INTEL_INFO(dev)->num_pipes; pipe++) { > + tmp = I915_READ(PF_CTL(pipe)); > + if (IS_GEN7(dev) && (tmp & PF_ENABLE) && > + PF_PIPE_SEL_IVB(pipe) != (tmp & PF_PIPE_SEL_MASK_IVB)) { > + DRM_DEBUG_KMS("disabling initial panel fitter\n"); > + I915_WRITE(PF_CTL(pipe), 0); > + I915_WRITE(PF_WIN_POS(pipe), 0); > + I915_WRITE(PF_WIN_SZ(pipe), 0); > + } > + } > > tmp = I915_READ(PF_CTL(crtc->pipe)); > > @@ -9177,14 +9195,6 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, > pipe_config->pch_pfit.enabled = true; > pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); > pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); > - > - /* We currently do not free assignements of panel fitters on > - * ivb/hsw (since we don't use the higher upscaling modes which > - * differentiates them) so just WARN about this case for now. */ > - if (IS_GEN7(dev)) { > - WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != > - PF_PIPE_SEL_IVB(crtc->pipe)); > - } > } > } -- Jani Nikula, Intel Open Source Technology Center