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s=dkim; t=1781271929; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=4kbuuuOZWUF1RFETFe0hK/FlP92aPI0TPvOQIoPd0E8=; b=xcIvkfGO6BEMQx4gfN2/H+Sa9bOcBUzyRTA7j5F3DAaNPQ+/ImEN3M+tplPXBhjQkmYBYU hLIjk8oORe2+mOx6efgWHaQ6lxJ3jF5bKQHAtniCl90GqD9YvFmpK1NnOb0UXw9843N2wt 2oU6ZbnPwkj0okTBk4e5tiChliEVEXJ2DENMJoHWvP+VxkbcatMjU/NijU0QZ89uAocdzH nysBLkApkGJ96Uxklp+RLr86FrbouBKVYNPP84+GJ3LqVn4QrK06ZIuMg10grsHaKo837E VC7z2NYTRhnJTWqMa5qJFvB6dLjvMsuYFZYUUrqEebg11KH2B6Q5AycJrqN8xw== From: Gregory CLEMENT To: Arnd Bergmann , Aleksander Jan Bajkowski , arm , soc@kernel.org Cc: Andrew Lunn , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org Subject: Re: [GIT PULL] ARM: mvebu: dt64 for v7.2 (#1) In-Reply-To: <8de15abe-8352-41f2-85c6-bdb50eb18e9a@app.fastmail.com> References: <8733z1c8uj.fsf@BLaptop.bootlin.com> <4e690104-b42f-4a2b-ac52-5ebfc82f6853@wp.pl> <956403e3-d47f-498c-9f62-79d39c1cf5db@app.fastmail.com> <8de15abe-8352-41f2-85c6-bdb50eb18e9a@app.fastmail.com> Date: Fri, 12 Jun 2026 15:45:26 +0200 Message-ID: <87o6hfc1op.fsf@BLaptop.bootlin.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Hello Arnd, > On Tue, Jun 9, 2026, at 21:29, Arnd Bergmann wrote: >> On Tue, Jun 9, 2026, at 19:35, Aleksander Jan Bajkowski wrote: >>> On 09/06/2026 18:11, Arnd Bergmann wrote: >>>> I'm a bit surprised by this oneline change. Since you successfully tes= ted >>>> this, I assume the change is correct, but I have two questions that >>>> I would like to have an answer for before I pull it. >>> By the way, the upstream safexcel driver works correctly only on=20 >>> coherent >>> platforms. On non-coherent platforms (MediaTek), the SHA-384 and SHA-512 >>> selftests fail. Since the selftests pass on Armada's SoC, I assume I'm= =20 >>> right. >> >> It's not necessarily proof that this is correct, but it is quite likely. >> >> After checking the datasheet some more and finding that this should >> indeed be coherent everywhere, I remembered that even the old >> 32-bit Armada 370 had a coherency manager. At the time, we used a hack >> in arch/arm/mach-mvebu/coherency.c to mark all device nodes as coherent, >> since the original DTB did not contain the correct annotations. >> >> I suspect that the Armada 37xx started out with a copy of the >> old DT files and also never had the annotation, but then never >> had the same hack because arch/arm64 does not have platform >> specific code. > > After investigating a little more, I think the correct fix here > will be to mark all DMA masters in this SoC as dma-coherent. > I thought there was a way to do this for an entire system, > but I could not find that, so this likely has to be done > for each DMA master separately. Thanks for doing this research. I also checked the data in the datasheet before applying the patch, and it appears the platform is coherent. I was surprised that when we initially submitted the support request, Marvel didn't mention this; usually, SoC vendors like to have good performance numbers. However, they also didn't say anything about a coherence issue. The fact that the test succeeded is a good indicator that the SoC is indeed coherent. > > Not sure who still has the hardware and has time to > test this properly. Given that the incorrect DT has > existed for over 10 years now, I assume this is not > urgent and I will skip the pull request for 7.2. I believe I still have a board based on an Armada 3700, and I should be able to find time to do some tests. Gregory > > Arnd --=20 Gr=C3=A9gory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com