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Thu, 29 Jan 2026 06:36:36 -0800 (PST) Received: from draig.lan ([185.124.0.126]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e131ce93sm14535267f8f.24.2026.01.29.06.36.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 06:36:35 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 0A4965F878; Thu, 29 Jan 2026 14:36:35 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Manos Pitsidianakis Subject: Re: [PATCH v2 2/6] target/arm: Report correct vector width in gdbstub when SME present In-Reply-To: <20260129113455.1283266-3-peter.maydell@linaro.org> (Peter Maydell's message of "Thu, 29 Jan 2026 11:34:51 +0000") References: <20260129113455.1283266-1-peter.maydell@linaro.org> <20260129113455.1283266-3-peter.maydell@linaro.org> User-Agent: mu4e 1.14.0-pre1; emacs 30.1 Date: Thu, 29 Jan 2026 14:36:34 +0000 Message-ID: <87o6mc8ozx.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Peter Maydell writes: > Our gdbstub implementation of the org.gnu.gdb.aarch64.sve feature > doesn't account for SME correctly. We always report the Zn vector > registers with a width based on the maximum SVE vector register size, > even though SME's maximum size could be larger. > > This is particularly bad in the case of a CPU with SME but not SVE, > because there the SVE vector width will be zero. If we report the Zn > registers in the XML as having a zero width then gdb falls over with > an internal error: > > (gdb) target remote :1234 > Remote debugging using :1234 > /build/gdb-1WjiBe/gdb-15.0.50.20240403/gdb/aarch64-tdep.c:3066: internal= -error: aarch64_pseudo_register_type: bad register number 160 > A problem internal to GDB has been detected, > further debugging may prove unreliable. > > Report the Zn registers with their correct size. This matches how we > already handle the 'vg' pseudoregister in org.gnu.gdb.aarch64.sve: we > call sve_vqm1_for_el(), which returns the vector size accounting for > SME, not the pure SVE vector size. > > Cc: qemu-stable@nongnu.org > Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro