From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org
Subject: Re: [PATCH 4/4] target/arm: Rename access_aa64_tid5() to access_tid5()
Date: Fri, 02 Jan 2026 11:21:34 +0000 [thread overview]
Message-ID: <87o6ncw98h.fsf@draig.linaro.org> (raw)
In-Reply-To: <20251231170858.254594-5-peter.maydell@linaro.org> (Peter Maydell's message of "Wed, 31 Dec 2025 17:08:58 +0000")
Peter Maydell <peter.maydell@linaro.org> writes:
> There is no equivalent access_aa32_tid5() (HCR_EL2.TID5 only exists
> starting from v8); rename access_aa64_tid5() to access_tid5() to line
> up with the naming we now have for the TID1 and TID3 check functions.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2026-01-02 11:21 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-31 17:08 [PATCH 0/4] target/arm: Fix handling of HCR.TID* on v7A CPUs Peter Maydell
2025-12-31 17:08 ` [PATCH 1/4] target/arm: Don't specify ID_PFR1 accessfn twice Peter Maydell
2026-01-02 10:56 ` Alex Bennée
2026-01-05 3:57 ` Richard Henderson
2025-12-31 17:08 ` [PATCH 2/4] target/arm: Correctly honour HCR.TID3 for v7A cores Peter Maydell
2026-01-02 11:17 ` Alex Bennée
2026-01-12 18:51 ` Peter Maydell
2026-01-15 15:20 ` Alex Bennée
2026-01-15 15:35 ` Peter Maydell
2026-01-15 15:54 ` Alex Bennée
2026-01-05 4:27 ` Richard Henderson
2025-12-31 17:08 ` [PATCH 3/4] target/arm: Correctly trap HCR.TID1 registers in v7A Peter Maydell
2026-01-02 11:21 ` Alex Bennée
2026-01-05 4:29 ` Richard Henderson
2025-12-31 17:08 ` [PATCH 4/4] target/arm: Rename access_aa64_tid5() to access_tid5() Peter Maydell
2026-01-02 11:21 ` Alex Bennée [this message]
2026-01-05 4:30 ` Richard Henderson
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