From: Jani Nikula <jani.nikula@linux.intel.com>
To: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, uma.shankar@intel.com,
chaitanya.kumar.borah@intel.com, animesh.manna@intel.com
Subject: Re: [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align()
Date: Wed, 14 May 2025 14:16:38 +0300 [thread overview]
Message-ID: <87o6vvh27d.fsf@intel.com> (raw)
In-Reply-To: <20250407142359.1398410-2-chaitanya.kumar.borah@intel.com>
On Mon, 07 Apr 2025, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract the code that alings the next instruction to the next
> QW boundary into a small helper. I'll have some more uses for
> this later.
>
> Also explain why we don't have to zero out the extra DW.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Chaitanya, your Signed-off-by is *required* in addition.
See https://developercertificate.org/.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0ddcdedf5453..c166e02b8af0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -228,13 +228,25 @@ static bool is_dsb_busy(struct intel_display *display, enum pipe pipe,
> return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY;
> }
>
> +static void intel_dsb_ins_align(struct intel_dsb *dsb)
> +{
> + /*
> + * Every instruction should be 8 byte aligned.
> + *
> + * The only way to get unaligned free_pos is via
> + * intel_dsb_reg_write_indexed() which already
> + * makes sure the next dword is zeroed, so no need
> + * to clear it here.
> + */
> + dsb->free_pos = ALIGN(dsb->free_pos, 2);
> +}
> +
> static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
> {
> if (!assert_dsb_has_room(dsb))
> return;
>
> - /* Every instruction should be 8 byte aligned. */
> - dsb->free_pos = ALIGN(dsb->free_pos, 2);
> + intel_dsb_ins_align(dsb);
>
> dsb->ins_start_offset = dsb->free_pos;
> dsb->ins[0] = ldw;
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-05-14 11:16 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-07 14:23 [PATCH 00/11] drm/xe/display: Program double buffered LUT registers Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align() Chaitanya Kumar Borah
2025-05-14 8:01 ` Shankar, Uma
2025-05-14 11:16 ` Jani Nikula [this message]
2025-05-14 11:58 ` Borah, Chaitanya Kumar
2025-04-07 14:23 ` [PATCH 02/11] drm/i915/dsb: Extract assert_dsb_tail_is_aligned() Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 03/11] drm/i915/dsb: Extract intel_dsb_{head,tail}() Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 04/11] drm/i915/dsb: Implement intel_dsb_gosub() Chaitanya Kumar Borah
2025-05-14 9:18 ` Shankar, Uma
2025-04-07 14:23 ` [PATCH 05/11] drm/i915/dsb: add intel_dsb_gosub_finish() Chaitanya Kumar Borah
2025-04-07 16:19 ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 06/11] drm/i915/dsb: Add support for GOSUB interrupt Chaitanya Kumar Borah
2025-04-07 16:30 ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 07/11] drm/i915: s/dsb_color_vblank/dsb_color Chaitanya Kumar Borah
2025-04-07 16:39 ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 08/11] drm/i915: use GOSUB to program doubled buffered LUT registers Chaitanya Kumar Borah
2025-04-07 16:51 ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 09/11] drm/i915: Program DB LUT registers before vblank Chaitanya Kumar Borah
2025-04-07 16:54 ` Ville Syrjälä
2025-04-07 14:23 ` [PATCH 10/11] drm/i915/color: Do not pre-load LUTs with DB registers Chaitanya Kumar Borah
2025-04-07 14:23 ` [PATCH 11/11] drm/i915: Disable updating of LUT values during vblank Chaitanya Kumar Borah
2025-04-07 14:49 ` ✓ CI.Patch_applied: success for drm/xe/display: Program double buffered LUT registers (rev5) Patchwork
2025-04-07 14:49 ` ✓ CI.checkpatch: " Patchwork
2025-04-07 14:50 ` ✓ CI.KUnit: " Patchwork
2025-04-07 14:54 ` ✗ CI.Build: failure " Patchwork
2025-04-07 17:05 ` ✗ Fi.CI.SPARSE: warning " Patchwork
2025-04-07 17:28 ` ✓ i915.CI.BAT: success " Patchwork
2025-04-07 19:32 ` ✗ i915.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-04-08 11:00 [PATCH 00/11] drm/xe/display: Program double buffered LUT registers Chaitanya Kumar Borah
2025-04-08 11:00 ` [PATCH 01/11] drm/i915/dsb: Extract intel_dsb_ins_align() Chaitanya Kumar Borah
2025-04-21 12:40 ` Manna, Animesh
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