From: Fabiano Rosas <farosas@suse.de>
To: Alistair Francis <alistair23@gmail.com>,
Ivan Klokov <ivan.klokov@syntacore.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, lvivier@redhat.com,
pbonzini@redhat.com
Subject: Re: [PATCH v9 0/2] Support RISC-V CSR read/write in Qtest environment
Date: Fri, 31 Jan 2025 09:19:47 -0300 [thread overview]
Message-ID: <87o6znkwf0.fsf@suse.de> (raw)
In-Reply-To: <CAKmqyKNgPj+o3X6rN5-ru2jMfH3VHPLP094CAhbDA8_JJEE+gA@mail.gmail.com>
Alistair Francis <alistair23@gmail.com> writes:
> On Thu, Jan 9, 2025 at 7:13 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>>
>> These patches add functionality for unit testing RISC-V-specific registers.
>> The first patch adds a Qtest backend, and the second implements a simple test.
>>
>> ---
>> v9:
>> - Fix build errors.
>> v8:
>> - Delete RFC label.
>> v7:
>> - Fix build errors, add Reviewed-by, Acked-by.
>> ---
>>
>> Ivan Klokov (2):
>> target/riscv: Add RISC-V CSR qtest support
>> tests/qtest: QTest example for RISC-V CSR register
>
> Do you mind rebasing on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next ?
>
This was already merged via the qtest tree. I forgot to post a message
to this thread, sorry.
prev parent reply other threads:[~2025-01-31 12:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-09 9:10 [PATCH v9 0/2] Support RISC-V CSR read/write in Qtest environment Ivan Klokov
2025-01-09 9:10 ` [PATCH v9 1/2] target/riscv: Add RISC-V CSR qtest support Ivan Klokov
2025-01-09 9:10 ` [PATCH v9 2/2] tests/qtest: QTest example for RISC-V CSR register Ivan Klokov
2025-01-31 0:36 ` [PATCH v9 0/2] Support RISC-V CSR read/write in Qtest environment Alistair Francis
2025-01-31 12:19 ` Fabiano Rosas [this message]
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