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From: Thomas Gleixner <tglx@linutronix.de>
To: Changhuang Liang <changhuang.liang@starfivetech.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>
Cc: Leyfoon Tan <leyfoon.tan@starfivetech.com>,
	Jack Zhu <jack.zhu@starfivetech.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: 回复: [PATCH v2 2/2] irqchip: Add StarFive external interrupt controller
Date: Tue, 20 Feb 2024 10:28:02 +0100	[thread overview]
Message-ID: <87o7cbiixp.ffs@tglx> (raw)
In-Reply-To: <SHXPR01MB0671BD046F6E3F3A215414A6F252A@SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn>

On Sun, Feb 18 2024 at 02:36, Changhuang Liang wrote:
>> On Mon, Jan 29 2024 at 21:58, Changhuang Liang wrote:
> [...]
>> > +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32
>> > +reg, u32 mask, u32 data) {
>> > +	u32 value;
>> > +
>> > +	value = ioread32(irqc->base + reg) & ~mask;
>> > +	data &= mask;
>> 
>> Why?
>> 
>
> If I want to update the reg  GENMASK(7, 4)  to value 5, the data I
> will pass in 5 << 4

All call sites pass a single bit to set/clear, right? So this GENMASK
argument does not make sense at all.

Thanks,

        tglx

  reply	other threads:[~2024-02-20  9:28 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-30  5:58 [PATCH v2 0/2] Add JH8100 external interrupt controller support Changhuang Liang
2024-01-30  5:58 ` [PATCH v2 1/2] dt-bindings: interrupt-controller: Add starfive,jh8100-intc Changhuang Liang
2024-01-30  5:58 ` [PATCH v2 2/2] irqchip: Add StarFive external interrupt controller Changhuang Liang
2024-02-13  9:03   ` Thomas Gleixner
2024-02-18  2:36     ` 回复: " Changhuang Liang
2024-02-20  9:28       ` Thomas Gleixner [this message]
2024-02-20  9:39         ` 回复: " Changhuang Liang

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