From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58539CD4F2B for ; Fri, 22 Sep 2023 08:37:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232589AbjIVIhf (ORCPT ); Fri, 22 Sep 2023 04:37:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232644AbjIVIhe (ORCPT ); Fri, 22 Sep 2023 04:37:34 -0400 Received: from mail.tkos.co.il (guitar.tkos.co.il [84.110.109.230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26F2383; Fri, 22 Sep 2023 01:37:25 -0700 (PDT) Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id BDA834402F4; Fri, 22 Sep 2023 11:37:09 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1695371830; bh=vIZ0eAo0ZmCv5PzYLGlwppRBM/hXM+Vo9RHfZHfNdRg=; h=References:From:To:Cc:Subject:Date:In-reply-to:From; b=lWw7J3TW9x4cc1prITpsNhZy0Xz4UJRO2v9gqD99Km/DT/EP73dVfvJKJKh1X987C CH4/a7MSGrNfzxiy+/Q2deaNg+vG4nbPvU1986dVWoA0GrfQZfAM4jjA1fCqx1uUDw 6SGhpUXzZFG3m7XLeBlyQ84CztpKRIa5Orv/ejyZbrVYq0A2z51ceh1P7RO68w+Xeq 1uWSOyY7HIx05/abmQHt3Npt9biz5eE1aCwWE4BLwaJW1MCWluEf1YXJdN6R9ZUVqa 7oF3vipzvMhyK22+pccl6cBNNX3NxVZu82ulbKLTVb/0Q5zYZddwSK82UxpWd0ty15 X5h0G7pzyEI1g== References: <17dd231f496d09ed8502bdd505eaa77bb6637e4b.1644226245.git.baruch@tkos.co.il> <8a331c88-c7d4-3a14-0ec3-fd616ea24a99@quicinc.com> <87wmwsylup.fsf@tarshish> <7b453ce7-7f41-12e7-9c7b-6c7d597037f2@quicinc.com> User-agent: mu4e 1.9.21; emacs 29.1 From: Baruch Siach To: Devi Priya Cc: Thierry Reding , Uwe =?utf-8?Q?Kleine-K?= =?utf-8?Q?=C3=B6nig?= , Andy Gross , Bjorn Andersson , Rob Herring , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] pwm: driver for qualcomm ipq6018 pwm block Date: Fri, 22 Sep 2023 11:35:33 +0300 In-reply-to: <7b453ce7-7f41-12e7-9c7b-6c7d597037f2@quicinc.com> Message-ID: <87o7huli2m.fsf@tarshish> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Devi, On Fri, Sep 22 2023, Devi Priya wrote: > On 9/15/2023 12:06 PM, Baruch Siach wrote: >> Hi Devi, >> [ Dropped/updated codeaurora.org addresses ] >> On Fri, Sep 15 2023, Devi Priya wrote: >>> On 2/7/2022 3:00 PM, Baruch Siach wrote: >>>> From: Baruch Siach >>>> Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on >>>> driver from downstream Codeaurora kernel tree. Removed support for old= er >>>> (V1) variants because I have no access to that hardware. >>>> Tested on IPQ6010 based hardware. >>>> Signed-off-by: Baruch Siach >>>> --- >>>> v11: >>> >>> Just curious to know if you have plans to post the next revision! >> I have been waiting for comments from pwm maintainers before sending the >> next revision. >> Unfortunately since then I lost access to the hardware, so I can't test >> suggested implementation changes. The only pending issue in v11 is the >> trivial change that Nathan Chancellor suggested, which should be safe. >> If you like to take it from here you are welcome. > > Could you pls point me to the pending comment that has to be addressed. > Was not able to find any open comments in the latest series. > https://lore.kernel.org/linux-arm-msm/8a331c88-c7d4-3a14-0ec3-fd616ea24a9= 9@quicinc.com/ See here: https://lore.kernel.org/all/YgK63cI177ZeF5v1@dev-arch.archlinux-ax161/ baruch >>>> Address comment from Uwe Kleine-K=C3=B6nig: >>>> Drop redundant registers field comments >>>> Fix period limit check in .apply >>>> Clarify the comment explaining skip of pre_div > pwm_div values >>>> Add explicit check for clock rate within limit >>>> Add comment explaining the selection of initial pre_div >>>> Use pwm_div division with remainder instead of separate diff calcu= lation >>>> Round up duty_cycle calculation in .get_state >>>> v10: >>>> Restore round up in pwm_div calculation; otherwise diff is always = <=3D >>>> 0, so only bingo match works >>>> Don't overwrite min_diff on every loop iteration >>>> v9: >>>> Address comment from Uwe Kleine-K=C3=B6nig: >>>> Use period_ns*rate in dividers calculation for better accuracy >>>> Round down pre_div and pwm_div >>>> Add a comment explaining why pwm_div can't underflow >>>> Add a comment explaining why pre_div > pwm_div end the search loop >>>> Drop 'CFG_' from register macros >>>> Rename to_ipq_pwm_chip() to ipq_pwm_from_chip() >>>> Change bare 'unsigned' to 'unsigned int' >>>> Clarify the comment on separate REG1 write for enable/disable >>>> Round up the period value in .get_state >>>> Use direct readl/writel so no need to check for regmap errors >>>> v7: >>>> Change 'offset' to 'reg' for the tcsr offset (Rob) >>>> Drop clock name; there is only one clock (Bjorn) >>>> Simplify probe failure code path (Bjorn) >>>> v6: >>>> Address Uwe Kleine-K=C3=B6nig review comments: >>>> Drop IPQ_PWM_MAX_DEVICES >>>> Rely on assigned-clock-rates; drop IPQ_PWM_CLK_SRC_FREQ >>>> Simplify register offset calculation >>>> Calculate duty cycle more precisely >>>> Refuse to set inverted polarity >>>> Drop redundant IPQ_PWM_REG1_ENABLE bit clear >>>> Remove x1000 factor in pwm_div calculation, use rate directly, and= round >>>> up >>>> Choose initial pre_div such that pwm_div < IPQ_PWM_MAX_DIV >>>> Ensure pre_div <=3D pwm_div >>>> Rename close_ to best_ >>>> Explain in comment why effective_div doesn't overflow >>>> Limit pwm_div to IPQ_PWM_MAX_DIV - 1 to allow 100% duty cycle >>>> Disable clock only after pwmchip_remove() >>>> const pwm_ops >>>> Other changes: >>>> Add missing linux/bitfield.h header include (kernel test robot) >>>> Adjust code for PWM device node under TCSR (Rob Herring) >>>> v5: >>>> Use &tcsr_q6 syscon to access registers (Bjorn Andersson) >>>> Address Uwe Kleine-K=C3=B6nig review comments: >>>> Implement .get_state() >>>> Add IPQ_PWM_ prefix to local macros >>>> Use GENMASK/BIT/FIELD_PREP for register fields access >>>> Make type of config_div_and_duty() parameters consistent >>>> Derive IPQ_PWM_MIN_PERIOD_NS from IPQ_PWM_CLK_SRC_FREQ >>>> Integrate enable/disable into config_div_and_duty() to save regist= er >>>> read, >>>> and reduce frequency glitch on update >>>> Use min() instead of min_t() >>>> Fix comment format >>>> Use dev_err_probe() to indicate probe step failure >>>> Add missing clk_disable_unprepare() in .remove >>>> Don't set .owner >>>> v4: >>>> Use div64_u64() to fix link for 32-bit targets ((kernel test robot >>>> , Uwe Kleine-K=C3=B6nig) >>>> v3: >>>> s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) >>>> Fix integer overflow on 32-bit targets (kernel test robot >>>> ) >>>> v2: >>>> Address Uwe Kleine-K=C3=B6nig review comments: >>>> Fix period calculation when out of range >>>> Don't set period larger than requested >>>> Remove PWM disable on configuration change >>>> Implement .apply instead of non-atomic .config/.enable/.disable >>>> Don't modify PWM on .request/.free >>>> Check pwm_div underflow >>>> Fix various code and comment formatting issues >>>> Other changes: >>>> Use u64 divisor safe division >>>> Remove now empty .request/.free >>>> --- >>>> drivers/pwm/Kconfig | 12 ++ >>>> drivers/pwm/Makefile | 1 + >>>> drivers/pwm/pwm-ipq.c | 281 +++++++++++++++++++++++++++++++++++++++= +++ >>>> 3 files changed, 294 insertions(+) >>>> create mode 100644 drivers/pwm/pwm-ipq.c >>>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig >>>> index 21e3b05a5153..e39718137ecd 100644 >>>> --- a/drivers/pwm/Kconfig >>>> +++ b/drivers/pwm/Kconfig >>>> @@ -260,6 +260,18 @@ config PWM_INTEL_LGM >>>> To compile this driver as a module, choose M here: the module >>>> will be called pwm-intel-lgm. >>>> +config PWM_IPQ >>>> + tristate "IPQ PWM support" >>>> + depends on ARCH_QCOM || COMPILE_TEST >>>> + depends on HAVE_CLK && HAS_IOMEM >>>> + help >>>> + Generic PWM framework driver for IPQ PWM block which supports >>>> + 4 pwm channels. Each of the these channels can be configured >>>> + independent of each other. >>>> + >>>> + To compile this driver as a module, choose M here: the module >>>> + will be called pwm-ipq. >>>> + >>>> config PWM_IQS620A >>>> tristate "Azoteq IQS620A PWM support" >>>> depends on MFD_IQS62X || COMPILE_TEST >>>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile >>>> index 708840b7fba8..7402feae4b36 100644 >>>> --- a/drivers/pwm/Makefile >>>> +++ b/drivers/pwm/Makefile >>>> @@ -22,6 +22,7 @@ obj-$(CONFIG_PWM_IMX1) +=3D pwm-imx1.o >>>> obj-$(CONFIG_PWM_IMX27) +=3D pwm-imx27.o >>>> obj-$(CONFIG_PWM_IMX_TPM) +=3D pwm-imx-tpm.o >>>> obj-$(CONFIG_PWM_INTEL_LGM) +=3D pwm-intel-lgm.o >>>> +obj-$(CONFIG_PWM_IPQ) +=3D pwm-ipq.o >>>> obj-$(CONFIG_PWM_IQS620A) +=3D pwm-iqs620a.o >>>> obj-$(CONFIG_PWM_JZ4740) +=3D pwm-jz4740.o >>>> obj-$(CONFIG_PWM_KEEMBAY) +=3D pwm-keembay.o >>>> diff --git a/drivers/pwm/pwm-ipq.c b/drivers/pwm/pwm-ipq.c >>>> new file mode 100644 >>>> index 000000000000..994027290bcb >>>> --- /dev/null >>>> +++ b/drivers/pwm/pwm-ipq.c >>>> @@ -0,0 +1,281 @@ >>>> +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 >>>> +/* >>>> + * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights res= erved. >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> +/* The frequency range supported is 1 Hz to clock rate */ >>>> +#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC) >>>> + >>>> +/* >>>> + * The max value specified for each field is based on the number of b= its >>>> + * in the pwm control register for that field >>>> + */ >>>> +#define IPQ_PWM_MAX_DIV 0xFFFF >>>> + >>>> +/* >>>> + * Two 32-bit registers for each PWM: REG0, and REG1. >>>> + * Base offset for PWM #i is at 8 * #i. >>>> + */ >>>> +#define IPQ_PWM_REG0 0 >>>> +#define IPQ_PWM_REG0_PWM_DIV GENMASK(15, 0) >>>> +#define IPQ_PWM_REG0_HI_DURATION GENMASK(31, 16) >>>> + >>>> +#define IPQ_PWM_REG1 4 >>>> +#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0) >>>> +/* >>>> + * Enable bit is set to enable output toggling in pwm device. >>>> + * Update bit is set to reflect the changed divider and high duration >>>> + * values in register. >>>> + */ >>>> +#define IPQ_PWM_REG1_UPDATE BIT(30) >>>> +#define IPQ_PWM_REG1_ENABLE BIT(31) >>>> + >>>> + >>>> +struct ipq_pwm_chip { >>>> + struct pwm_chip chip; >>>> + struct clk *clk; >>>> + void __iomem *mem; >>>> +}; >>>> + >>>> +static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip) >>>> +{ >>>> + return container_of(chip, struct ipq_pwm_chip, chip); >>>> +} >>>> + >>>> +static unsigned int ipq_pwm_reg_read(struct pwm_device *pwm, unsigned= int reg) >>>> +{ >>>> + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); >>>> + unsigned int off =3D 8 * pwm->hwpwm + reg; >>>> + >>>> + return readl(ipq_chip->mem + off); >>>> +} >>>> + >>>> +static void ipq_pwm_reg_write(struct pwm_device *pwm, unsigned int re= g, >>>> + unsigned int val) >>>> +{ >>>> + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(pwm->chip); >>>> + unsigned int off =3D 8 * pwm->hwpwm + reg; >>>> + >>>> + writel(val, ipq_chip->mem + off); >>>> +} >>>> + >>>> +static void config_div_and_duty(struct pwm_device *pwm, unsigned int = pre_div, >>>> + unsigned int pwm_div, unsigned long rate, u64 duty_ns, >>>> + bool enable) >>>> +{ >>>> + unsigned long hi_dur; >>>> + unsigned long val =3D 0; >>>> + >>>> + /* >>>> + * high duration =3D pwm duty * (pwm div + 1) >>>> + * pwm duty =3D duty_ns / period_ns >>>> + */ >>>> + hi_dur =3D div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC); >>>> + >>>> + val =3D FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) | >>>> + FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div); >>>> + ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val); >>>> + >>>> + val =3D FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div); >>>> + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); >>>> + >>>> + /* PWM enable toggle needs a separate write to REG1 */ >>>> + val |=3D IPQ_PWM_REG1_UPDATE; >>>> + if (enable) >>>> + val |=3D IPQ_PWM_REG1_ENABLE; >>>> + ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val); >>>> +} >>>> + >>>> +static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pw= m, >>>> + const struct pwm_state *state) >>>> +{ >>>> + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); >>>> + unsigned int pre_div, pwm_div, best_pre_div, best_pwm_div; >>>> + unsigned long rate =3D clk_get_rate(ipq_chip->clk); >>>> + u64 period_ns, duty_ns, period_rate; >>>> + u64 min_diff; >>>> + >>>> + if (state->polarity !=3D PWM_POLARITY_NORMAL) >>>> + return -EINVAL; >>>> + >>>> + if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate)) >>>> + return -ERANGE; >>>> + >>>> + period_ns =3D min(state->period, IPQ_PWM_MAX_PERIOD_NS); >>>> + duty_ns =3D min(state->duty_cycle, period_ns); >>>> + >>>> + /* >>>> + * period_ns is 1G or less. As long as rate is less than 16 GHz, >>>> + * period_rate does not overflow. Make that explicit. >>>> + */ >>>> + if (rate > 16ULL * GIGA) >>>> + return -EINVAL; >>>> + period_rate =3D period_ns * rate; >>>> + best_pre_div =3D IPQ_PWM_MAX_DIV; >>>> + best_pwm_div =3D IPQ_PWM_MAX_DIV; >>>> + /* >>>> + * We don't need to consider pre_div values smaller than >>>> + * >>>> + * period_rate >>>> + * pre_div_min :=3D ------------------------------------ >>>> + * NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1) >>>> + * >>>> + * because pre_div =3D pre_div_min results in a better >>>> + * approximation. >>>> + */ >>>> + pre_div =3D div64_u64(period_rate, >>>> + (u64)NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1)); >>>> + min_diff =3D period_rate; >>>> + >>>> + for (; pre_div <=3D IPQ_PWM_MAX_DIV; pre_div++) { >>>> + u64 remainder; >>>> + >>>> + pwm_div =3D div64_u64_rem(period_rate, >>>> + (u64)NSEC_PER_SEC * (pre_div + 1), &remainder); >>>> + /* pwm_div is unsigned; the check below catches underflow */ >>>> + pwm_div--; >>>> + >>>> + /* >>>> + * Swapping values for pre_div and pwm_div produces the same >>>> + * period length. So we can skip all settings with pre_div > >>>> + * pwm_div which results in bigger constraints for selecting >>>> + * the duty_cycle than with the two values swapped. >>>> + */ >>>> + if (pre_div > pwm_div) >>>> + break; >>>> + >>>> + /* >>>> + * Make sure we can do 100% duty cycle where >>>> + * hi_dur =3D=3D pwm_div + 1 >>>> + */ >>>> + if (pwm_div > IPQ_PWM_MAX_DIV - 1) >>>> + continue; >>>> + >>>> + if (remainder < min_diff) { >>>> + best_pre_div =3D pre_div; >>>> + best_pwm_div =3D pwm_div; >>>> + min_diff =3D remainder; >>>> + >>>> + if (min_diff =3D=3D 0) /* bingo */ >>>> + break; >>>> + } >>>> + } >>>> + >>>> + /* config divider values for the closest possible frequency */ >>>> + config_div_and_duty(pwm, best_pre_div, best_pwm_div, >>>> + rate, duty_ns, state->enabled); >>>> + >>>> + return 0; >>>> +} >>>> + >>>> +static void ipq_pwm_get_state(struct pwm_chip *chip, struct pwm_devic= e *pwm, >>>> + struct pwm_state *state) >>>> +{ >>>> + struct ipq_pwm_chip *ipq_chip =3D ipq_pwm_from_chip(chip); >>>> + unsigned long rate =3D clk_get_rate(ipq_chip->clk); >>>> + unsigned int pre_div, pwm_div, hi_dur; >>>> + u64 effective_div, hi_div; >>>> + u32 reg0, reg1; >>>> + >>>> + reg0 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG0); >>>> + reg1 =3D ipq_pwm_reg_read(pwm, IPQ_PWM_REG1); >>>> + >>>> + state->polarity =3D PWM_POLARITY_NORMAL; >>>> + state->enabled =3D reg1 & IPQ_PWM_REG1_ENABLE; >>>> + >>>> + pwm_div =3D FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0); >>>> + hi_dur =3D FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0); >>>> + pre_div =3D FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1); >>>> + >>>> + /* No overflow here, both pre_div and pwm_div <=3D 0xffff */ >>>> + effective_div =3D (u64)(pre_div + 1) * (pwm_div + 1); >>>> + state->period =3D DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, r= ate); >>>> + >>>> + hi_div =3D hi_dur * (pre_div + 1); >>>> + state->duty_cycle =3D DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate= ); >>>> +} >>>> + >>>> +static const struct pwm_ops ipq_pwm_ops =3D { >>>> + .apply =3D ipq_pwm_apply, >>>> + .get_state =3D ipq_pwm_get_state, >>>> + .owner =3D THIS_MODULE, >>>> +}; >>>> + >>>> +static int ipq_pwm_probe(struct platform_device *pdev) >>>> +{ >>>> + struct ipq_pwm_chip *pwm; >>>> + struct device *dev =3D &pdev->dev; >>>> + int ret; >>>> + >>>> + pwm =3D devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); >>>> + if (!pwm) >>>> + return -ENOMEM; >>>> + >>>> + platform_set_drvdata(pdev, pwm); >>>> + >>>> + pwm->mem =3D devm_platform_ioremap_resource(pdev, 0); >>>> + if (IS_ERR(pwm->mem)) >>>> + return dev_err_probe(dev, PTR_ERR(pwm->mem), >>>> + "regs map failed"); >>>> + >>>> + pwm->clk =3D devm_clk_get(dev, NULL); >>>> + if (IS_ERR(pwm->clk)) >>>> + return dev_err_probe(dev, PTR_ERR(pwm->clk), >>>> + "failed to get clock"); >>>> + >>>> + ret =3D clk_prepare_enable(pwm->clk); >>>> + if (ret) >>>> + return dev_err_probe(dev, ret, "clock enable failed"); >>>> + >>>> + pwm->chip.dev =3D dev; >>>> + pwm->chip.ops =3D &ipq_pwm_ops; >>>> + pwm->chip.npwm =3D 4; >>>> + >>>> + ret =3D pwmchip_add(&pwm->chip); >>>> + if (ret < 0) { >>>> + dev_err_probe(dev, ret, "pwmchip_add() failed\n"); >>>> + clk_disable_unprepare(pwm->clk); >>>> + } >>>> + >>>> + return ret; >>>> +} >>>> + >>>> +static int ipq_pwm_remove(struct platform_device *pdev) >>>> +{ >>>> + struct ipq_pwm_chip *pwm =3D platform_get_drvdata(pdev); >>>> + >>>> + pwmchip_remove(&pwm->chip); >>>> + clk_disable_unprepare(pwm->clk); >>>> + >>>> + return 0; >>>> +} >>>> + >>>> +static const struct of_device_id pwm_ipq_dt_match[] =3D { >>>> + { .compatible =3D "qcom,ipq6018-pwm", }, >>>> + {} >>>> +}; >>>> +MODULE_DEVICE_TABLE(of, pwm_ipq_dt_match); >>>> + >>>> +static struct platform_driver ipq_pwm_driver =3D { >>>> + .driver =3D { >>>> + .name =3D "ipq-pwm", >>>> + .of_match_table =3D pwm_ipq_dt_match, >>>> + }, >>>> + .probe =3D ipq_pwm_probe, >>>> + .remove =3D ipq_pwm_remove, >>>> +}; >>>> + >>>> +module_platform_driver(ipq_pwm_driver); >>>> + >>>> +MODULE_LICENSE("Dual BSD/GPL"); >>=20 --=20 ~. .~ Tk Open Systems =3D}------------------------------------------------ooO--U--Ooo------------= {=3D - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il - From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A75ECD4F32 for ; Fri, 22 Sep 2023 08:38:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:In-reply-to: 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User-agent: mu4e 1.9.21; emacs 29.1 From: Baruch Siach To: Devi Priya Cc: Thierry Reding , Uwe =?utf-8?Q?Kleine-K?= =?utf-8?Q?=C3=B6nig?= , Andy Gross , Bjorn Andersson , Rob Herring , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] pwm: driver for qualcomm ipq6018 pwm block Date: Fri, 22 Sep 2023 11:35:33 +0300 In-reply-to: <7b453ce7-7f41-12e7-9c7b-6c7d597037f2@quicinc.com> Message-ID: <87o7huli2m.fsf@tarshish> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230922_013732_845970_1ED0A084 X-CRM114-Status: GOOD ( 32.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgRGV2aSwKCk9uIEZyaSwgU2VwIDIyIDIwMjMsIERldmkgUHJpeWEgd3JvdGU6Cj4gT24gOS8x NS8yMDIzIDEyOjA2IFBNLCBCYXJ1Y2ggU2lhY2ggd3JvdGU6Cj4+IEhpIERldmksCj4+IFsgRHJv cHBlZC91cGRhdGVkIGNvZGVhdXJvcmEub3JnIGFkZHJlc3NlcyBdCj4+IE9uIEZyaSwgU2VwIDE1 IDIwMjMsIERldmkgUHJpeWEgd3JvdGU6Cj4+PiBPbiAyLzcvMjAyMiAzOjAwIFBNLCBCYXJ1Y2gg U2lhY2ggd3JvdGU6Cj4+Pj4gRnJvbTogQmFydWNoIFNpYWNoIDxiYXJ1Y2guc2lhY2hAc2lrbHUu Y29tPgo+Pj4+IERyaXZlciBmb3IgdGhlIFBXTSBibG9jayBpbiBRdWFsY29tbSBJUFE2MDE4IGxp bmUgb2YgU29Dcy4gQmFzZWQgb24KPj4+PiBkcml2ZXIgZnJvbSBkb3duc3RyZWFtIENvZGVhdXJv cmEga2VybmVsIHRyZWUuIFJlbW92ZWQgc3VwcG9ydCBmb3Igb2xkZXIKPj4+PiAoVjEpIHZhcmlh bnRzIGJlY2F1c2UgSSBoYXZlIG5vIGFjY2VzcyB0byB0aGF0IGhhcmR3YXJlLgo+Pj4+IFRlc3Rl ZCBvbiBJUFE2MDEwIGJhc2VkIGhhcmR3YXJlLgo+Pj4+IFNpZ25lZC1vZmYtYnk6IEJhcnVjaCBT aWFjaCA8YmFydWNoLnNpYWNoQHNpa2x1LmNvbT4KPj4+PiAtLS0KPj4+PiB2MTE6Cj4+Pgo+Pj4g SnVzdCBjdXJpb3VzIHRvIGtub3cgaWYgeW91IGhhdmUgcGxhbnMgdG8gcG9zdCB0aGUgbmV4dCBy ZXZpc2lvbiEKPj4gSSBoYXZlIGJlZW4gd2FpdGluZyBmb3IgY29tbWVudHMgZnJvbSBwd20gbWFp bnRhaW5lcnMgYmVmb3JlIHNlbmRpbmcgdGhlCj4+IG5leHQgcmV2aXNpb24uCj4+IFVuZm9ydHVu YXRlbHkgc2luY2UgdGhlbiBJIGxvc3QgYWNjZXNzIHRvIHRoZSBoYXJkd2FyZSwgc28gSSBjYW4n dCB0ZXN0Cj4+IHN1Z2dlc3RlZCBpbXBsZW1lbnRhdGlvbiBjaGFuZ2VzLiAgVGhlIG9ubHkgcGVu ZGluZyBpc3N1ZSBpbiB2MTEgaXMgdGhlCj4+IHRyaXZpYWwgY2hhbmdlIHRoYXQgTmF0aGFuIENo YW5jZWxsb3Igc3VnZ2VzdGVkLCB3aGljaCBzaG91bGQgYmUgc2FmZS4KPj4gSWYgeW91IGxpa2Ug dG8gdGFrZSBpdCBmcm9tIGhlcmUgeW91IGFyZSB3ZWxjb21lLgo+Cj4gQ291bGQgeW91IHBscyBw b2ludCBtZSB0byB0aGUgcGVuZGluZyBjb21tZW50IHRoYXQgaGFzIHRvIGJlIGFkZHJlc3NlZC4K PiBXYXMgbm90IGFibGUgdG8gZmluZCBhbnkgb3BlbiBjb21tZW50cyBpbiB0aGUgbGF0ZXN0IHNl cmllcy4KPiBodHRwczovL2xvcmUua2VybmVsLm9yZy9saW51eC1hcm0tbXNtLzhhMzMxYzg4LWM3 ZDQtM2ExNC0wZWMzLWZkNjE2ZWEyNGE5OUBxdWljaW5jLmNvbS8KClNlZSBoZXJlOgoKICBodHRw czovL2xvcmUua2VybmVsLm9yZy9hbGwvWWdLNjNjSTE3N1plRjV2MUBkZXYtYXJjaC5hcmNobGlu dXgtYXgxNjEvCgpiYXJ1Y2gKCj4+Pj4gQWRkcmVzcyBjb21tZW50IGZyb20gVXdlIEtsZWluZS1L w7ZuaWc6Cj4+Pj4gICAgIERyb3AgcmVkdW5kYW50IHJlZ2lzdGVycyBmaWVsZCBjb21tZW50cwo+ Pj4+ICAgICBGaXggcGVyaW9kIGxpbWl0IGNoZWNrIGluIC5hcHBseQo+Pj4+ICAgICBDbGFyaWZ5 IHRoZSBjb21tZW50IGV4cGxhaW5pbmcgc2tpcCBvZiBwcmVfZGl2ID4gcHdtX2RpdiB2YWx1ZXMK Pj4+PiAgICAgQWRkIGV4cGxpY2l0IGNoZWNrIGZvciBjbG9jayByYXRlIHdpdGhpbiBsaW1pdAo+ Pj4+ICAgICBBZGQgY29tbWVudCBleHBsYWluaW5nIHRoZSBzZWxlY3Rpb24gb2YgaW5pdGlhbCBw cmVfZGl2Cj4+Pj4gICAgIFVzZSBwd21fZGl2IGRpdmlzaW9uIHdpdGggcmVtYWluZGVyIGluc3Rl YWQgb2Ygc2VwYXJhdGUgZGlmZiBjYWxjdWxhdGlvbgo+Pj4+ICAgICBSb3VuZCB1cCBkdXR5X2N5 Y2xlIGNhbGN1bGF0aW9uIGluIC5nZXRfc3RhdGUKPj4+PiB2MTA6Cj4+Pj4gICAgIFJlc3RvcmUg cm91bmQgdXAgaW4gcHdtX2RpdiBjYWxjdWxhdGlvbjsgb3RoZXJ3aXNlIGRpZmYgaXMgYWx3YXlz IDw9Cj4+Pj4gICAgIDAsIHNvIG9ubHkgYmluZ28gbWF0Y2ggd29ya3MKPj4+PiAgICAgRG9uJ3Qg b3ZlcndyaXRlIG1pbl9kaWZmIG9uIGV2ZXJ5IGxvb3AgaXRlcmF0aW9uCj4+Pj4gdjk6Cj4+Pj4g QWRkcmVzcyBjb21tZW50IGZyb20gVXdlIEtsZWluZS1Lw7ZuaWc6Cj4+Pj4gICAgIFVzZSBwZXJp b2RfbnMqcmF0ZSBpbiBkaXZpZGVycyBjYWxjdWxhdGlvbiBmb3IgYmV0dGVyIGFjY3VyYWN5Cj4+ Pj4gICAgIFJvdW5kIGRvd24gcHJlX2RpdiBhbmQgcHdtX2Rpdgo+Pj4+ICAgICBBZGQgYSBjb21t ZW50IGV4cGxhaW5pbmcgd2h5IHB3bV9kaXYgY2FuJ3QgdW5kZXJmbG93Cj4+Pj4gICAgIEFkZCBh IGNvbW1lbnQgZXhwbGFpbmluZyB3aHkgcHJlX2RpdiA+IHB3bV9kaXYgZW5kIHRoZSBzZWFyY2gg bG9vcAo+Pj4+ICAgICBEcm9wICdDRkdfJyBmcm9tIHJlZ2lzdGVyIG1hY3Jvcwo+Pj4+ICAgICBS ZW5hbWUgdG9faXBxX3B3bV9jaGlwKCkgdG8gaXBxX3B3bV9mcm9tX2NoaXAoKQo+Pj4+ICAgICBD aGFuZ2UgYmFyZSAndW5zaWduZWQnIHRvICd1bnNpZ25lZCBpbnQnCj4+Pj4gICAgIENsYXJpZnkg dGhlIGNvbW1lbnQgb24gc2VwYXJhdGUgUkVHMSB3cml0ZSBmb3IgZW5hYmxlL2Rpc2FibGUKPj4+ PiAgICAgUm91bmQgdXAgdGhlIHBlcmlvZCB2YWx1ZSBpbiAuZ2V0X3N0YXRlCj4+Pj4gICAgIFVz ZSBkaXJlY3QgcmVhZGwvd3JpdGVsIHNvIG5vIG5lZWQgdG8gY2hlY2sgZm9yIHJlZ21hcCBlcnJv cnMKPj4+PiB2NzoKPj4+PiAgICAgQ2hhbmdlICdvZmZzZXQnIHRvICdyZWcnIGZvciB0aGUgdGNz ciBvZmZzZXQgKFJvYikKPj4+PiAgICAgRHJvcCBjbG9jayBuYW1lOyB0aGVyZSBpcyBvbmx5IG9u ZSBjbG9jayAoQmpvcm4pCj4+Pj4gICAgIFNpbXBsaWZ5IHByb2JlIGZhaWx1cmUgY29kZSBwYXRo IChCam9ybikKPj4+PiB2NjoKPj4+PiBBZGRyZXNzIFV3ZSBLbGVpbmUtS8O2bmlnIHJldmlldyBj b21tZW50czoKPj4+PiAgICAgRHJvcCBJUFFfUFdNX01BWF9ERVZJQ0VTCj4+Pj4gICAgIFJlbHkg b24gYXNzaWduZWQtY2xvY2stcmF0ZXM7IGRyb3AgSVBRX1BXTV9DTEtfU1JDX0ZSRVEKPj4+PiAg ICAgU2ltcGxpZnkgcmVnaXN0ZXIgb2Zmc2V0IGNhbGN1bGF0aW9uCj4+Pj4gICAgIENhbGN1bGF0 ZSBkdXR5IGN5Y2xlIG1vcmUgcHJlY2lzZWx5Cj4+Pj4gICAgIFJlZnVzZSB0byBzZXQgaW52ZXJ0 ZWQgcG9sYXJpdHkKPj4+PiAgICAgRHJvcCByZWR1bmRhbnQgSVBRX1BXTV9SRUcxX0VOQUJMRSBi aXQgY2xlYXIKPj4+PiAgICAgUmVtb3ZlIHgxMDAwIGZhY3RvciBpbiBwd21fZGl2IGNhbGN1bGF0 aW9uLCB1c2UgcmF0ZSBkaXJlY3RseSwgYW5kIHJvdW5kCj4+Pj4gdXAKPj4+PiAgICAgQ2hvb3Nl IGluaXRpYWwgcHJlX2RpdiBzdWNoIHRoYXQgcHdtX2RpdiA8IElQUV9QV01fTUFYX0RJVgo+Pj4+ ICAgICBFbnN1cmUgcHJlX2RpdiA8PSBwd21fZGl2Cj4+Pj4gICAgIFJlbmFtZSBjbG9zZV8gdG8g YmVzdF8KPj4+PiAgICAgRXhwbGFpbiBpbiBjb21tZW50IHdoeSBlZmZlY3RpdmVfZGl2IGRvZXNu J3Qgb3ZlcmZsb3cKPj4+PiAgICAgTGltaXQgcHdtX2RpdiB0byBJUFFfUFdNX01BWF9ESVYgLSAx IHRvIGFsbG93IDEwMCUgZHV0eSBjeWNsZQo+Pj4+ICAgICBEaXNhYmxlIGNsb2NrIG9ubHkgYWZ0 ZXIgcHdtY2hpcF9yZW1vdmUoKQo+Pj4+ICAgICBjb25zdCBwd21fb3BzCj4+Pj4gT3RoZXIgY2hh bmdlczoKPj4+PiAgICAgQWRkIG1pc3NpbmcgbGludXgvYml0ZmllbGQuaCBoZWFkZXIgaW5jbHVk ZSAoa2VybmVsIHRlc3Qgcm9ib3QpCj4+Pj4gICAgIEFkanVzdCBjb2RlIGZvciBQV00gZGV2aWNl IG5vZGUgdW5kZXIgVENTUiAoUm9iIEhlcnJpbmcpCj4+Pj4gdjU6Cj4+Pj4gVXNlICZ0Y3NyX3E2 IHN5c2NvbiB0byBhY2Nlc3MgcmVnaXN0ZXJzIChCam9ybiBBbmRlcnNzb24pCj4+Pj4gQWRkcmVz cyBVd2UgS2xlaW5lLUvDtm5pZyByZXZpZXcgY29tbWVudHM6Cj4+Pj4gICAgIEltcGxlbWVudCAu Z2V0X3N0YXRlKCkKPj4+PiAgICAgQWRkIElQUV9QV01fIHByZWZpeCB0byBsb2NhbCBtYWNyb3MK Pj4+PiAgICAgVXNlIEdFTk1BU0svQklUL0ZJRUxEX1BSRVAgZm9yIHJlZ2lzdGVyIGZpZWxkcyBh Y2Nlc3MKPj4+PiAgICAgTWFrZSB0eXBlIG9mIGNvbmZpZ19kaXZfYW5kX2R1dHkoKSBwYXJhbWV0 ZXJzIGNvbnNpc3RlbnQKPj4+PiAgICAgRGVyaXZlIElQUV9QV01fTUlOX1BFUklPRF9OUyBmcm9t IElQUV9QV01fQ0xLX1NSQ19GUkVRCj4+Pj4gICAgIEludGVncmF0ZSBlbmFibGUvZGlzYWJsZSBp bnRvIGNvbmZpZ19kaXZfYW5kX2R1dHkoKSB0byBzYXZlIHJlZ2lzdGVyCj4+Pj4gcmVhZCwKPj4+ PiAgICAgYW5kIHJlZHVjZSBmcmVxdWVuY3kgZ2xpdGNoIG9uIHVwZGF0ZQo+Pj4+ICAgICBVc2Ug bWluKCkgaW5zdGVhZCBvZiBtaW5fdCgpCj4+Pj4gICAgIEZpeCBjb21tZW50IGZvcm1hdAo+Pj4+ ICAgICBVc2UgZGV2X2Vycl9wcm9iZSgpIHRvIGluZGljYXRlIHByb2JlIHN0ZXAgZmFpbHVyZQo+ Pj4+ICAgICBBZGQgbWlzc2luZyBjbGtfZGlzYWJsZV91bnByZXBhcmUoKSBpbiAucmVtb3ZlCj4+ Pj4gICAgIERvbid0IHNldCAub3duZXIKPj4+PiB2NDoKPj4+PiAgICAgVXNlIGRpdjY0X3U2NCgp IHRvIGZpeCBsaW5rIGZvciAzMi1iaXQgdGFyZ2V0cyAoKGtlcm5lbCB0ZXN0IHJvYm90Cj4+Pj4g ICAgIDxsa3BAaW50ZWwuY29tPiwgVXdlIEtsZWluZS1Lw7ZuaWcpCj4+Pj4gdjM6Cj4+Pj4gICAg IHMvcWNvbSxwd20taXBxNjAxOC9xY29tLGlwcTYwMTgtcHdtLyAoUm9iIEhlcnJpbmcpCj4+Pj4g ICAgIEZpeCBpbnRlZ2VyIG92ZXJmbG93IG9uIDMyLWJpdCB0YXJnZXRzIChrZXJuZWwgdGVzdCBy b2JvdAo+Pj4+IDxsa3BAaW50ZWwuY29tPikKPj4+PiB2MjoKPj4+PiBBZGRyZXNzIFV3ZSBLbGVp bmUtS8O2bmlnIHJldmlldyBjb21tZW50czoKPj4+PiAgICAgRml4IHBlcmlvZCBjYWxjdWxhdGlv biB3aGVuIG91dCBvZiByYW5nZQo+Pj4+ICAgICBEb24ndCBzZXQgcGVyaW9kIGxhcmdlciB0aGFu IHJlcXVlc3RlZAo+Pj4+ICAgICBSZW1vdmUgUFdNIGRpc2FibGUgb24gY29uZmlndXJhdGlvbiBj aGFuZ2UKPj4+PiAgICAgSW1wbGVtZW50IC5hcHBseSBpbnN0ZWFkIG9mIG5vbi1hdG9taWMgLmNv bmZpZy8uZW5hYmxlLy5kaXNhYmxlCj4+Pj4gICAgIERvbid0IG1vZGlmeSBQV00gb24gLnJlcXVl c3QvLmZyZWUKPj4+PiAgICAgQ2hlY2sgcHdtX2RpdiB1bmRlcmZsb3cKPj4+PiAgICAgRml4IHZh cmlvdXMgY29kZSBhbmQgY29tbWVudCBmb3JtYXR0aW5nIGlzc3Vlcwo+Pj4+IE90aGVyIGNoYW5n ZXM6Cj4+Pj4gICAgIFVzZSB1NjQgZGl2aXNvciBzYWZlIGRpdmlzaW9uCj4+Pj4gICAgIFJlbW92 ZSBub3cgZW1wdHkgLnJlcXVlc3QvLmZyZWUKPj4+PiAtLS0KPj4+PiAgICBkcml2ZXJzL3B3bS9L Y29uZmlnICAgfCAgMTIgKysKPj4+PiAgICBkcml2ZXJzL3B3bS9NYWtlZmlsZSAgfCAgIDEgKwo+ Pj4+ICAgIGRyaXZlcnMvcHdtL3B3bS1pcHEuYyB8IDI4MSArKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysKPj4+PiAgICAzIGZpbGVzIGNoYW5nZWQsIDI5NCBpbnNlcnRp b25zKCspCj4+Pj4gICAgY3JlYXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvcHdtL3B3bS1pcHEuYwo+ Pj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3B3bS9LY29uZmlnIGIvZHJpdmVycy9wd20vS2NvbmZp Zwo+Pj4+IGluZGV4IDIxZTNiMDVhNTE1My4uZTM5NzE4MTM3ZWNkIDEwMDY0NAo+Pj4+IC0tLSBh L2RyaXZlcnMvcHdtL0tjb25maWcKPj4+PiArKysgYi9kcml2ZXJzL3B3bS9LY29uZmlnCj4+Pj4g QEAgLTI2MCw2ICsyNjAsMTggQEAgY29uZmlnIFBXTV9JTlRFTF9MR00KPj4+PiAgICAJICBUbyBj b21waWxlIHRoaXMgZHJpdmVyIGFzIGEgbW9kdWxlLCBjaG9vc2UgTSBoZXJlOiB0aGUgbW9kdWxl Cj4+Pj4gICAgCSAgd2lsbCBiZSBjYWxsZWQgcHdtLWludGVsLWxnbS4KPj4+PiAgICArY29uZmln IFBXTV9JUFEKPj4+PiArCXRyaXN0YXRlICJJUFEgUFdNIHN1cHBvcnQiCj4+Pj4gKwlkZXBlbmRz IG9uIEFSQ0hfUUNPTSB8fCBDT01QSUxFX1RFU1QKPj4+PiArCWRlcGVuZHMgb24gSEFWRV9DTEsg JiYgSEFTX0lPTUVNCj4+Pj4gKwloZWxwCj4+Pj4gKwkgIEdlbmVyaWMgUFdNIGZyYW1ld29yayBk cml2ZXIgZm9yIElQUSBQV00gYmxvY2sgd2hpY2ggc3VwcG9ydHMKPj4+PiArCSAgNCBwd20gY2hh bm5lbHMuIEVhY2ggb2YgdGhlIHRoZXNlIGNoYW5uZWxzIGNhbiBiZSBjb25maWd1cmVkCj4+Pj4g KwkgIGluZGVwZW5kZW50IG9mIGVhY2ggb3RoZXIuCj4+Pj4gKwo+Pj4+ICsJICBUbyBjb21waWxl IHRoaXMgZHJpdmVyIGFzIGEgbW9kdWxlLCBjaG9vc2UgTSBoZXJlOiB0aGUgbW9kdWxlCj4+Pj4g KwkgIHdpbGwgYmUgY2FsbGVkIHB3bS1pcHEuCj4+Pj4gKwo+Pj4+ICAgIGNvbmZpZyBQV01fSVFT NjIwQQo+Pj4+ICAgIAl0cmlzdGF0ZSAiQXpvdGVxIElRUzYyMEEgUFdNIHN1cHBvcnQiCj4+Pj4g ICAgCWRlcGVuZHMgb24gTUZEX0lRUzYyWCB8fCBDT01QSUxFX1RFU1QKPj4+PiBkaWZmIC0tZ2l0 IGEvZHJpdmVycy9wd20vTWFrZWZpbGUgYi9kcml2ZXJzL3B3bS9NYWtlZmlsZQo+Pj4+IGluZGV4 IDcwODg0MGI3ZmJhOC4uNzQwMmZlYWU0YjM2IDEwMDY0NAo+Pj4+IC0tLSBhL2RyaXZlcnMvcHdt L01ha2VmaWxlCj4+Pj4gKysrIGIvZHJpdmVycy9wd20vTWFrZWZpbGUKPj4+PiBAQCAtMjIsNiAr MjIsNyBAQCBvYmotJChDT05GSUdfUFdNX0lNWDEpCQkrPSBwd20taW14MS5vCj4+Pj4gICAgb2Jq LSQoQ09ORklHX1BXTV9JTVgyNykJCSs9IHB3bS1pbXgyNy5vCj4+Pj4gICAgb2JqLSQoQ09ORklH X1BXTV9JTVhfVFBNKQkrPSBwd20taW14LXRwbS5vCj4+Pj4gICAgb2JqLSQoQ09ORklHX1BXTV9J TlRFTF9MR00pCSs9IHB3bS1pbnRlbC1sZ20ubwo+Pj4+ICtvYmotJChDT05GSUdfUFdNX0lQUSkJ CSs9IHB3bS1pcHEubwo+Pj4+ICAgIG9iai0kKENPTkZJR19QV01fSVFTNjIwQSkJKz0gcHdtLWlx czYyMGEubwo+Pj4+ICAgIG9iai0kKENPTkZJR19QV01fSlo0NzQwKQkrPSBwd20tano0NzQwLm8K Pj4+PiAgICBvYmotJChDT05GSUdfUFdNX0tFRU1CQVkpCSs9IHB3bS1rZWVtYmF5Lm8KPj4+PiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9wd20vcHdtLWlwcS5jIGIvZHJpdmVycy9wd20vcHdtLWlwcS5j Cj4+Pj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPj4+PiBpbmRleCAwMDAwMDAwMDAwMDAuLjk5NDAy NzI5MGJjYgo+Pj4+IC0tLSAvZGV2L251bGwKPj4+PiArKysgYi9kcml2ZXJzL3B3bS9wd20taXBx LmMKPj4+PiBAQCAtMCwwICsxLDI4MSBAQAo+Pj4+ICsvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmll cjogQlNELTMtQ2xhdXNlIE9SIEdQTC0yLjAKPj4+PiArLyoKPj4+PiArICogQ29weXJpZ2h0IChj KSAyMDE2LTIwMTcsIDIwMjAgVGhlIExpbnV4IEZvdW5kYXRpb24uIEFsbCByaWdodHMgcmVzZXJ2 ZWQuCj4+Pj4gKyAqLwo+Pj4+ICsKPj4+PiArI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+Pj4+ ICsjaW5jbHVkZSA8bGludXgvcGxhdGZvcm1fZGV2aWNlLmg+Cj4+Pj4gKyNpbmNsdWRlIDxsaW51 eC9wd20uaD4KPj4+PiArI2luY2x1ZGUgPGxpbnV4L2Nsay5oPgo+Pj4+ICsjaW5jbHVkZSA8bGlu dXgvaW8uaD4KPj4+PiArI2luY2x1ZGUgPGxpbnV4L29mLmg+Cj4+Pj4gKyNpbmNsdWRlIDxsaW51 eC9tYXRoNjQuaD4KPj4+PiArI2luY2x1ZGUgPGxpbnV4L29mX2RldmljZS5oPgo+Pj4+ICsjaW5j bHVkZSA8bGludXgvYml0ZmllbGQuaD4KPj4+PiArI2luY2x1ZGUgPGxpbnV4L3VuaXRzLmg+Cj4+ Pj4gKwo+Pj4+ICsvKiBUaGUgZnJlcXVlbmN5IHJhbmdlIHN1cHBvcnRlZCBpcyAxIEh6IHRvIGNs b2NrIHJhdGUgKi8KPj4+PiArI2RlZmluZSBJUFFfUFdNX01BWF9QRVJJT0RfTlMJKCh1NjQpTlNF Q19QRVJfU0VDKQo+Pj4+ICsKPj4+PiArLyoKPj4+PiArICogVGhlIG1heCB2YWx1ZSBzcGVjaWZp ZWQgZm9yIGVhY2ggZmllbGQgaXMgYmFzZWQgb24gdGhlIG51bWJlciBvZiBiaXRzCj4+Pj4gKyAq IGluIHRoZSBwd20gY29udHJvbCByZWdpc3RlciBmb3IgdGhhdCBmaWVsZAo+Pj4+ICsgKi8KPj4+ PiArI2RlZmluZSBJUFFfUFdNX01BWF9ESVYJCTB4RkZGRgo+Pj4+ICsKPj4+PiArLyoKPj4+PiAr ICogVHdvIDMyLWJpdCByZWdpc3RlcnMgZm9yIGVhY2ggUFdNOiBSRUcwLCBhbmQgUkVHMS4KPj4+ PiArICogQmFzZSBvZmZzZXQgZm9yIFBXTSAjaSBpcyBhdCA4ICogI2kuCj4+Pj4gKyAqLwo+Pj4+ ICsjZGVmaW5lIElQUV9QV01fUkVHMAkJCTAKPj4+PiArI2RlZmluZSBJUFFfUFdNX1JFRzBfUFdN X0RJVgkJR0VOTUFTSygxNSwgMCkKPj4+PiArI2RlZmluZSBJUFFfUFdNX1JFRzBfSElfRFVSQVRJ T04JR0VOTUFTSygzMSwgMTYpCj4+Pj4gKwo+Pj4+ICsjZGVmaW5lIElQUV9QV01fUkVHMQkJCTQK Pj4+PiArI2RlZmluZSBJUFFfUFdNX1JFRzFfUFJFX0RJVgkJR0VOTUFTSygxNSwgMCkKPj4+PiAr LyoKPj4+PiArICogRW5hYmxlIGJpdCBpcyBzZXQgdG8gZW5hYmxlIG91dHB1dCB0b2dnbGluZyBp biBwd20gZGV2aWNlLgo+Pj4+ICsgKiBVcGRhdGUgYml0IGlzIHNldCB0byByZWZsZWN0IHRoZSBj aGFuZ2VkIGRpdmlkZXIgYW5kIGhpZ2ggZHVyYXRpb24KPj4+PiArICogdmFsdWVzIGluIHJlZ2lz dGVyLgo+Pj4+ICsgKi8KPj4+PiArI2RlZmluZSBJUFFfUFdNX1JFRzFfVVBEQVRFCQlCSVQoMzAp Cj4+Pj4gKyNkZWZpbmUgSVBRX1BXTV9SRUcxX0VOQUJMRQkJQklUKDMxKQo+Pj4+ICsKPj4+PiAr Cj4+Pj4gK3N0cnVjdCBpcHFfcHdtX2NoaXAgewo+Pj4+ICsJc3RydWN0IHB3bV9jaGlwIGNoaXA7 Cj4+Pj4gKwlzdHJ1Y3QgY2xrICpjbGs7Cj4+Pj4gKwl2b2lkIF9faW9tZW0gKm1lbTsKPj4+PiAr fTsKPj4+PiArCj4+Pj4gK3N0YXRpYyBzdHJ1Y3QgaXBxX3B3bV9jaGlwICppcHFfcHdtX2Zyb21f Y2hpcChzdHJ1Y3QgcHdtX2NoaXAgKmNoaXApCj4+Pj4gK3sKPj4+PiArCXJldHVybiBjb250YWlu ZXJfb2YoY2hpcCwgc3RydWN0IGlwcV9wd21fY2hpcCwgY2hpcCk7Cj4+Pj4gK30KPj4+PiArCj4+ Pj4gK3N0YXRpYyB1bnNpZ25lZCBpbnQgaXBxX3B3bV9yZWdfcmVhZChzdHJ1Y3QgcHdtX2Rldmlj ZSAqcHdtLCB1bnNpZ25lZCBpbnQgcmVnKQo+Pj4+ICt7Cj4+Pj4gKwlzdHJ1Y3QgaXBxX3B3bV9j aGlwICppcHFfY2hpcCA9IGlwcV9wd21fZnJvbV9jaGlwKHB3bS0+Y2hpcCk7Cj4+Pj4gKwl1bnNp Z25lZCBpbnQgb2ZmID0gOCAqIHB3bS0+aHdwd20gKyByZWc7Cj4+Pj4gKwo+Pj4+ICsJcmV0dXJu IHJlYWRsKGlwcV9jaGlwLT5tZW0gKyBvZmYpOwo+Pj4+ICt9Cj4+Pj4gKwo+Pj4+ICtzdGF0aWMg dm9pZCBpcHFfcHdtX3JlZ193cml0ZShzdHJ1Y3QgcHdtX2RldmljZSAqcHdtLCB1bnNpZ25lZCBp bnQgcmVnLAo+Pj4+ICsJCQkgICAgICB1bnNpZ25lZCBpbnQgdmFsKQo+Pj4+ICt7Cj4+Pj4gKwlz dHJ1Y3QgaXBxX3B3bV9jaGlwICppcHFfY2hpcCA9IGlwcV9wd21fZnJvbV9jaGlwKHB3bS0+Y2hp cCk7Cj4+Pj4gKwl1bnNpZ25lZCBpbnQgb2ZmID0gOCAqIHB3bS0+aHdwd20gKyByZWc7Cj4+Pj4g Kwo+Pj4+ICsJd3JpdGVsKHZhbCwgaXBxX2NoaXAtPm1lbSArIG9mZik7Cj4+Pj4gK30KPj4+PiAr Cj4+Pj4gK3N0YXRpYyB2b2lkIGNvbmZpZ19kaXZfYW5kX2R1dHkoc3RydWN0IHB3bV9kZXZpY2Ug KnB3bSwgdW5zaWduZWQgaW50IHByZV9kaXYsCj4+Pj4gKwkJCXVuc2lnbmVkIGludCBwd21fZGl2 LCB1bnNpZ25lZCBsb25nIHJhdGUsIHU2NCBkdXR5X25zLAo+Pj4+ICsJCQlib29sIGVuYWJsZSkK Pj4+PiArewo+Pj4+ICsJdW5zaWduZWQgbG9uZyBoaV9kdXI7Cj4+Pj4gKwl1bnNpZ25lZCBsb25n IHZhbCA9IDA7Cj4+Pj4gKwo+Pj4+ICsJLyoKPj4+PiArCSAqIGhpZ2ggZHVyYXRpb24gPSBwd20g ZHV0eSAqIChwd20gZGl2ICsgMSkKPj4+PiArCSAqIHB3bSBkdXR5ID0gZHV0eV9ucyAvIHBlcmlv ZF9ucwo+Pj4+ICsJICovCj4+Pj4gKwloaV9kdXIgPSBkaXY2NF91NjQoZHV0eV9ucyAqIHJhdGUs IChwcmVfZGl2ICsgMSkgKiBOU0VDX1BFUl9TRUMpOwo+Pj4+ICsKPj4+PiArCXZhbCA9IEZJRUxE X1BSRVAoSVBRX1BXTV9SRUcwX0hJX0RVUkFUSU9OLCBoaV9kdXIpIHwKPj4+PiArCQlGSUVMRF9Q UkVQKElQUV9QV01fUkVHMF9QV01fRElWLCBwd21fZGl2KTsKPj4+PiArCWlwcV9wd21fcmVnX3dy aXRlKHB3bSwgSVBRX1BXTV9SRUcwLCB2YWwpOwo+Pj4+ICsKPj4+PiArCXZhbCA9IEZJRUxEX1BS RVAoSVBRX1BXTV9SRUcxX1BSRV9ESVYsIHByZV9kaXYpOwo+Pj4+ICsJaXBxX3B3bV9yZWdfd3Jp dGUocHdtLCBJUFFfUFdNX1JFRzEsIHZhbCk7Cj4+Pj4gKwo+Pj4+ICsJLyogUFdNIGVuYWJsZSB0 b2dnbGUgbmVlZHMgYSBzZXBhcmF0ZSB3cml0ZSB0byBSRUcxICovCj4+Pj4gKwl2YWwgfD0gSVBR X1BXTV9SRUcxX1VQREFURTsKPj4+PiArCWlmIChlbmFibGUpCj4+Pj4gKwkJdmFsIHw9IElQUV9Q V01fUkVHMV9FTkFCTEU7Cj4+Pj4gKwlpcHFfcHdtX3JlZ193cml0ZShwd20sIElQUV9QV01fUkVH MSwgdmFsKTsKPj4+PiArfQo+Pj4+ICsKPj4+PiArc3RhdGljIGludCBpcHFfcHdtX2FwcGx5KHN0 cnVjdCBwd21fY2hpcCAqY2hpcCwgc3RydWN0IHB3bV9kZXZpY2UgKnB3bSwKPj4+PiArCQkJIGNv bnN0IHN0cnVjdCBwd21fc3RhdGUgKnN0YXRlKQo+Pj4+ICt7Cj4+Pj4gKwlzdHJ1Y3QgaXBxX3B3 bV9jaGlwICppcHFfY2hpcCA9IGlwcV9wd21fZnJvbV9jaGlwKGNoaXApOwo+Pj4+ICsJdW5zaWdu ZWQgaW50IHByZV9kaXYsIHB3bV9kaXYsIGJlc3RfcHJlX2RpdiwgYmVzdF9wd21fZGl2Owo+Pj4+ ICsJdW5zaWduZWQgbG9uZyByYXRlID0gY2xrX2dldF9yYXRlKGlwcV9jaGlwLT5jbGspOwo+Pj4+ ICsJdTY0IHBlcmlvZF9ucywgZHV0eV9ucywgcGVyaW9kX3JhdGU7Cj4+Pj4gKwl1NjQgbWluX2Rp ZmY7Cj4+Pj4gKwo+Pj4+ICsJaWYgKHN0YXRlLT5wb2xhcml0eSAhPSBQV01fUE9MQVJJVFlfTk9S TUFMKQo+Pj4+ICsJCXJldHVybiAtRUlOVkFMOwo+Pj4+ICsKPj4+PiArCWlmIChzdGF0ZS0+cGVy aW9kIDwgRElWNjRfVTY0X1JPVU5EX1VQKE5TRUNfUEVSX1NFQywgcmF0ZSkpCj4+Pj4gKwkJcmV0 dXJuIC1FUkFOR0U7Cj4+Pj4gKwo+Pj4+ICsJcGVyaW9kX25zID0gbWluKHN0YXRlLT5wZXJpb2Qs IElQUV9QV01fTUFYX1BFUklPRF9OUyk7Cj4+Pj4gKwlkdXR5X25zID0gbWluKHN0YXRlLT5kdXR5 X2N5Y2xlLCBwZXJpb2RfbnMpOwo+Pj4+ICsKPj4+PiArCS8qCj4+Pj4gKwkgKiBwZXJpb2RfbnMg aXMgMUcgb3IgbGVzcy4gQXMgbG9uZyBhcyByYXRlIGlzIGxlc3MgdGhhbiAxNiBHSHosCj4+Pj4g KwkgKiBwZXJpb2RfcmF0ZSBkb2VzIG5vdCBvdmVyZmxvdy4gTWFrZSB0aGF0IGV4cGxpY2l0Lgo+ Pj4+ICsJICovCj4+Pj4gKwlpZiAocmF0ZSA+IDE2VUxMICogR0lHQSkKPj4+PiArCQlyZXR1cm4g LUVJTlZBTDsKPj4+PiArCXBlcmlvZF9yYXRlID0gcGVyaW9kX25zICogcmF0ZTsKPj4+PiArCWJl c3RfcHJlX2RpdiA9IElQUV9QV01fTUFYX0RJVjsKPj4+PiArCWJlc3RfcHdtX2RpdiA9IElQUV9Q V01fTUFYX0RJVjsKPj4+PiArCS8qCj4+Pj4gKwkgKiBXZSBkb24ndCBuZWVkIHRvIGNvbnNpZGVy IHByZV9kaXYgdmFsdWVzIHNtYWxsZXIgdGhhbgo+Pj4+ICsJICoKPj4+PiArCSAqICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgcGVyaW9kX3JhdGUKPj4+PiArCSAqICBwcmVfZGl2X21pbiA6 PSAtLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KPj4+PiArCSAqICAgICAgICAg ICAgICAgICBOU0VDX1BFUl9TRUMgKiAoSVBRX1BXTV9NQVhfRElWICsgMSkKPj4+PiArCSAqCj4+ Pj4gKwkgKiBiZWNhdXNlIHByZV9kaXYgPSBwcmVfZGl2X21pbiByZXN1bHRzIGluIGEgYmV0dGVy Cj4+Pj4gKwkgKiBhcHByb3hpbWF0aW9uLgo+Pj4+ICsJICovCj4+Pj4gKwlwcmVfZGl2ID0gZGl2 NjRfdTY0KHBlcmlvZF9yYXRlLAo+Pj4+ICsJCQkodTY0KU5TRUNfUEVSX1NFQyAqIChJUFFfUFdN X01BWF9ESVYgKyAxKSk7Cj4+Pj4gKwltaW5fZGlmZiA9IHBlcmlvZF9yYXRlOwo+Pj4+ICsKPj4+ PiArCWZvciAoOyBwcmVfZGl2IDw9IElQUV9QV01fTUFYX0RJVjsgcHJlX2RpdisrKSB7Cj4+Pj4g KwkJdTY0IHJlbWFpbmRlcjsKPj4+PiArCj4+Pj4gKwkJcHdtX2RpdiA9IGRpdjY0X3U2NF9yZW0o cGVyaW9kX3JhdGUsCj4+Pj4gKwkJCQkodTY0KU5TRUNfUEVSX1NFQyAqIChwcmVfZGl2ICsgMSks ICZyZW1haW5kZXIpOwo+Pj4+ICsJCS8qIHB3bV9kaXYgaXMgdW5zaWduZWQ7IHRoZSBjaGVjayBi ZWxvdyBjYXRjaGVzIHVuZGVyZmxvdyAqLwo+Pj4+ICsJCXB3bV9kaXYtLTsKPj4+PiArCj4+Pj4g KwkJLyoKPj4+PiArCQkgKiBTd2FwcGluZyB2YWx1ZXMgZm9yIHByZV9kaXYgYW5kIHB3bV9kaXYg cHJvZHVjZXMgdGhlIHNhbWUKPj4+PiArCQkgKiBwZXJpb2QgbGVuZ3RoLiBTbyB3ZSBjYW4gc2tp cCBhbGwgc2V0dGluZ3Mgd2l0aCBwcmVfZGl2ID4KPj4+PiArCQkgKiBwd21fZGl2IHdoaWNoIHJl c3VsdHMgaW4gYmlnZ2VyIGNvbnN0cmFpbnRzIGZvciBzZWxlY3RpbmcKPj4+PiArCQkgKiB0aGUg ZHV0eV9jeWNsZSB0aGFuIHdpdGggdGhlIHR3byB2YWx1ZXMgc3dhcHBlZC4KPj4+PiArCQkgKi8K Pj4+PiArCQlpZiAocHJlX2RpdiA+IHB3bV9kaXYpCj4+Pj4gKwkJCWJyZWFrOwo+Pj4+ICsKPj4+ PiArCQkvKgo+Pj4+ICsJCSAqIE1ha2Ugc3VyZSB3ZSBjYW4gZG8gMTAwJSBkdXR5IGN5Y2xlIHdo ZXJlCj4+Pj4gKwkJICogaGlfZHVyID09IHB3bV9kaXYgKyAxCj4+Pj4gKwkJICovCj4+Pj4gKwkJ aWYgKHB3bV9kaXYgPiBJUFFfUFdNX01BWF9ESVYgLSAxKQo+Pj4+ICsJCQljb250aW51ZTsKPj4+ PiArCj4+Pj4gKwkJaWYgKHJlbWFpbmRlciA8IG1pbl9kaWZmKSB7Cj4+Pj4gKwkJCWJlc3RfcHJl X2RpdiA9IHByZV9kaXY7Cj4+Pj4gKwkJCWJlc3RfcHdtX2RpdiA9IHB3bV9kaXY7Cj4+Pj4gKwkJ CW1pbl9kaWZmID0gcmVtYWluZGVyOwo+Pj4+ICsKPj4+PiArCQkJaWYgKG1pbl9kaWZmID09IDAp IC8qIGJpbmdvICovCj4+Pj4gKwkJCQlicmVhazsKPj4+PiArCQl9Cj4+Pj4gKwl9Cj4+Pj4gKwo+ Pj4+ICsJLyogY29uZmlnIGRpdmlkZXIgdmFsdWVzIGZvciB0aGUgY2xvc2VzdCBwb3NzaWJsZSBm cmVxdWVuY3kgKi8KPj4+PiArCWNvbmZpZ19kaXZfYW5kX2R1dHkocHdtLCBiZXN0X3ByZV9kaXYs IGJlc3RfcHdtX2RpdiwKPj4+PiArCQkJICAgIHJhdGUsIGR1dHlfbnMsIHN0YXRlLT5lbmFibGVk KTsKPj4+PiArCj4+Pj4gKwlyZXR1cm4gMDsKPj4+PiArfQo+Pj4+ICsKPj4+PiArc3RhdGljIHZv aWQgaXBxX3B3bV9nZXRfc3RhdGUoc3RydWN0IHB3bV9jaGlwICpjaGlwLCBzdHJ1Y3QgcHdtX2Rl dmljZSAqcHdtLAo+Pj4+ICsJCQkgICAgICBzdHJ1Y3QgcHdtX3N0YXRlICpzdGF0ZSkKPj4+PiAr ewo+Pj4+ICsJc3RydWN0IGlwcV9wd21fY2hpcCAqaXBxX2NoaXAgPSBpcHFfcHdtX2Zyb21fY2hp cChjaGlwKTsKPj4+PiArCXVuc2lnbmVkIGxvbmcgcmF0ZSA9IGNsa19nZXRfcmF0ZShpcHFfY2hp cC0+Y2xrKTsKPj4+PiArCXVuc2lnbmVkIGludCBwcmVfZGl2LCBwd21fZGl2LCBoaV9kdXI7Cj4+ Pj4gKwl1NjQgZWZmZWN0aXZlX2RpdiwgaGlfZGl2Owo+Pj4+ICsJdTMyIHJlZzAsIHJlZzE7Cj4+ Pj4gKwo+Pj4+ICsJcmVnMCA9IGlwcV9wd21fcmVnX3JlYWQocHdtLCBJUFFfUFdNX1JFRzApOwo+ Pj4+ICsJcmVnMSA9IGlwcV9wd21fcmVnX3JlYWQocHdtLCBJUFFfUFdNX1JFRzEpOwo+Pj4+ICsK Pj4+PiArCXN0YXRlLT5wb2xhcml0eSA9IFBXTV9QT0xBUklUWV9OT1JNQUw7Cj4+Pj4gKwlzdGF0 ZS0+ZW5hYmxlZCA9IHJlZzEgJiBJUFFfUFdNX1JFRzFfRU5BQkxFOwo+Pj4+ICsKPj4+PiArCXB3 bV9kaXYgPSBGSUVMRF9HRVQoSVBRX1BXTV9SRUcwX1BXTV9ESVYsIHJlZzApOwo+Pj4+ICsJaGlf ZHVyID0gRklFTERfR0VUKElQUV9QV01fUkVHMF9ISV9EVVJBVElPTiwgcmVnMCk7Cj4+Pj4gKwlw cmVfZGl2ID0gRklFTERfR0VUKElQUV9QV01fUkVHMV9QUkVfRElWLCByZWcxKTsKPj4+PiArCj4+ Pj4gKwkvKiBObyBvdmVyZmxvdyBoZXJlLCBib3RoIHByZV9kaXYgYW5kIHB3bV9kaXYgPD0gMHhm ZmZmICovCj4+Pj4gKwllZmZlY3RpdmVfZGl2ID0gKHU2NCkocHJlX2RpdiArIDEpICogKHB3bV9k aXYgKyAxKTsKPj4+PiArCXN0YXRlLT5wZXJpb2QgPSBESVY2NF9VNjRfUk9VTkRfVVAoZWZmZWN0 aXZlX2RpdiAqIE5TRUNfUEVSX1NFQywgcmF0ZSk7Cj4+Pj4gKwo+Pj4+ICsJaGlfZGl2ID0gaGlf ZHVyICogKHByZV9kaXYgKyAxKTsKPj4+PiArCXN0YXRlLT5kdXR5X2N5Y2xlID0gRElWNjRfVTY0 X1JPVU5EX1VQKGhpX2RpdiAqIE5TRUNfUEVSX1NFQywgcmF0ZSk7Cj4+Pj4gK30KPj4+PiArCj4+ Pj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcHdtX29wcyBpcHFfcHdtX29wcyA9IHsKPj4+PiArCS5h cHBseSA9IGlwcV9wd21fYXBwbHksCj4+Pj4gKwkuZ2V0X3N0YXRlID0gaXBxX3B3bV9nZXRfc3Rh dGUsCj4+Pj4gKwkub3duZXIgPSBUSElTX01PRFVMRSwKPj4+PiArfTsKPj4+PiArCj4+Pj4gK3N0 YXRpYyBpbnQgaXBxX3B3bV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+Pj4+ ICt7Cj4+Pj4gKwlzdHJ1Y3QgaXBxX3B3bV9jaGlwICpwd207Cj4+Pj4gKwlzdHJ1Y3QgZGV2aWNl ICpkZXYgPSAmcGRldi0+ZGV2Owo+Pj4+ICsJaW50IHJldDsKPj4+PiArCj4+Pj4gKwlwd20gPSBk ZXZtX2t6YWxsb2MoZGV2LCBzaXplb2YoKnB3bSksIEdGUF9LRVJORUwpOwo+Pj4+ICsJaWYgKCFw d20pCj4+Pj4gKwkJcmV0dXJuIC1FTk9NRU07Cj4+Pj4gKwo+Pj4+ICsJcGxhdGZvcm1fc2V0X2Ry dmRhdGEocGRldiwgcHdtKTsKPj4+PiArCj4+Pj4gKwlwd20tPm1lbSA9IGRldm1fcGxhdGZvcm1f aW9yZW1hcF9yZXNvdXJjZShwZGV2LCAwKTsKPj4+PiArCWlmIChJU19FUlIocHdtLT5tZW0pKQo+ Pj4+ICsJCXJldHVybiBkZXZfZXJyX3Byb2JlKGRldiwgUFRSX0VSUihwd20tPm1lbSksCj4+Pj4g KwkJCQkicmVncyBtYXAgZmFpbGVkIik7Cj4+Pj4gKwo+Pj4+ICsJcHdtLT5jbGsgPSBkZXZtX2Ns a19nZXQoZGV2LCBOVUxMKTsKPj4+PiArCWlmIChJU19FUlIocHdtLT5jbGspKQo+Pj4+ICsJCXJl dHVybiBkZXZfZXJyX3Byb2JlKGRldiwgUFRSX0VSUihwd20tPmNsayksCj4+Pj4gKwkJCQkiZmFp bGVkIHRvIGdldCBjbG9jayIpOwo+Pj4+ICsKPj4+PiArCXJldCA9IGNsa19wcmVwYXJlX2VuYWJs ZShwd20tPmNsayk7Cj4+Pj4gKwlpZiAocmV0KQo+Pj4+ICsJCXJldHVybiBkZXZfZXJyX3Byb2Jl KGRldiwgcmV0LCAiY2xvY2sgZW5hYmxlIGZhaWxlZCIpOwo+Pj4+ICsKPj4+PiArCXB3bS0+Y2hp cC5kZXYgPSBkZXY7Cj4+Pj4gKwlwd20tPmNoaXAub3BzID0gJmlwcV9wd21fb3BzOwo+Pj4+ICsJ cHdtLT5jaGlwLm5wd20gPSA0Owo+Pj4+ICsKPj4+PiArCXJldCA9IHB3bWNoaXBfYWRkKCZwd20t PmNoaXApOwo+Pj4+ICsJaWYgKHJldCA8IDApIHsKPj4+PiArCQlkZXZfZXJyX3Byb2JlKGRldiwg cmV0LCAicHdtY2hpcF9hZGQoKSBmYWlsZWRcbiIpOwo+Pj4+ICsJCWNsa19kaXNhYmxlX3VucHJl cGFyZShwd20tPmNsayk7Cj4+Pj4gKwl9Cj4+Pj4gKwo+Pj4+ICsJcmV0dXJuIHJldDsKPj4+PiAr fQo+Pj4+ICsKPj4+PiArc3RhdGljIGludCBpcHFfcHdtX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1f ZGV2aWNlICpwZGV2KQo+Pj4+ICt7Cj4+Pj4gKwlzdHJ1Y3QgaXBxX3B3bV9jaGlwICpwd20gPSBw bGF0Zm9ybV9nZXRfZHJ2ZGF0YShwZGV2KTsKPj4+PiArCj4+Pj4gKwlwd21jaGlwX3JlbW92ZSgm cHdtLT5jaGlwKTsKPj4+PiArCWNsa19kaXNhYmxlX3VucHJlcGFyZShwd20tPmNsayk7Cj4+Pj4g Kwo+Pj4+ICsJcmV0dXJuIDA7Cj4+Pj4gK30KPj4+PiArCj4+Pj4gK3N0YXRpYyBjb25zdCBzdHJ1 Y3Qgb2ZfZGV2aWNlX2lkIHB3bV9pcHFfZHRfbWF0Y2hbXSA9IHsKPj4+PiArCXsgLmNvbXBhdGli bGUgPSAicWNvbSxpcHE2MDE4LXB3bSIsIH0sCj4+Pj4gKwl7fQo+Pj4+ICt9Owo+Pj4+ICtNT0RV TEVfREVWSUNFX1RBQkxFKG9mLCBwd21faXBxX2R0X21hdGNoKTsKPj4+PiArCj4+Pj4gK3N0YXRp YyBzdHJ1Y3QgcGxhdGZvcm1fZHJpdmVyIGlwcV9wd21fZHJpdmVyID0gewo+Pj4+ICsJLmRyaXZl ciA9IHsKPj4+PiArCQkubmFtZSA9ICJpcHEtcHdtIiwKPj4+PiArCQkub2ZfbWF0Y2hfdGFibGUg PSBwd21faXBxX2R0X21hdGNoLAo+Pj4+ICsJfSwKPj4+PiArCS5wcm9iZSA9IGlwcV9wd21fcHJv YmUsCj4+Pj4gKwkucmVtb3ZlID0gaXBxX3B3bV9yZW1vdmUsCj4+Pj4gK307Cj4+Pj4gKwo+Pj4+ ICttb2R1bGVfcGxhdGZvcm1fZHJpdmVyKGlwcV9wd21fZHJpdmVyKTsKPj4+PiArCj4+Pj4gK01P RFVMRV9MSUNFTlNFKCJEdWFsIEJTRC9HUEwiKTsKPj4gCgoKLS0gCiAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgfi4gLn4gICBUayBPcGVuIFN5c3Rl bXMKPX0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS1vb08t LVUtLU9vby0tLS0tLS0tLS0tLXs9CiAgIC0gYmFydWNoQHRrb3MuY28uaWwgLSB0ZWw6ICs5NzIu NTIuMzY4LjQ2NTYsIGh0dHA6Ly93d3cudGtvcy5jby5pbCAtCgpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlz dApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJh ZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2VybmVsCg==