From: Jani Nikula <jani.nikula@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: ville.syrjala@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
Date: Tue, 10 Jan 2023 18:10:48 +0200 [thread overview]
Message-ID: <87o7r6id4n.fsf@intel.com> (raw)
In-Reply-To: <Y72GF2CgEVDElPwD@mdroper-desk1.amr.corp.intel.com>
On Tue, 10 Jan 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Tue, Jan 10, 2023 at 11:06:14AM +0200, Jani Nikula wrote:
>> On Sat, 07 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
>> > @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>> > /* Wa_22011320316:adl-p[a0] */
>> > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> > dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
>>
>> Are RPL-U A0-B0 going to enter this branch? Is this the right thing to
>> do?
>
> There's no such thing as a RPL A0/B0. RPL continues the stepping
> progression from ADL, and all RPL parts have E0 or newer display
> steppings (bspec 55376).
Ok, thanks.
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2023-01-10 16:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-07 5:36 ` [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform Chaitanya Kumar Borah
2023-01-10 1:02 ` Matt Roper
2023-01-12 9:45 ` Borah, Chaitanya Kumar
2023-01-07 5:36 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-10 1:08 ` Matt Roper
2023-01-12 9:48 ` Borah, Chaitanya Kumar
2023-01-10 9:06 ` Jani Nikula
2023-01-10 15:36 ` Matt Roper
2023-01-10 16:10 ` Jani Nikula [this message]
2023-01-07 5:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev3) Patchwork
2023-01-07 8:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-07 9:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps " Chaitanya Kumar Borah
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step " Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps " Chaitanya Kumar Borah
2023-01-24 14:33 ` Jani Nikula
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