Re: [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK

From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, Deepak M <m.deepak@intel.com>
Subject: Re: [GLK MIPI DSI V5 2/8] drm/i915/glk: Program new MIPI DSI PHY registers for GLK
Date: Thu, 16 Feb 2017 16:50:25 +0200	[thread overview]
Message-ID: <87o9y2mbpq.fsf@intel.com> (raw)
In-Reply-To: <1487078180-15147-3-git-send-email-madhav.chauhan@intel.com>

On Tue, 14 Feb 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Program the clk lane and tlpx time count registers
> to configure DSI PHY.
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Program clk lane timing reg same as dphy param reg.
> v4: Removed "line over 80 character" warning
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 8 ++++++++
>  drivers/gpu/drm/i915/intel_dsi.c | 8 ++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 141a5c1..c09f665 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8636,6 +8636,14 @@ enum {
>  #define  LP_BYTECLK_SHIFT				0
>  #define  LP_BYTECLK_MASK				(0xffff << 0)
>  
> +#define _MIPIA_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb0a4)
> +#define _MIPIC_TLPX_TIME_COUNT		(dev_priv->mipi_mmio_base + 0xb8a4)
> +#define MIPI_TLPX_TIME_COUNT(port)	 _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
> +
> +#define _MIPIA_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb098)
> +#define _MIPIC_CLK_LANE_TIMING		(dev_priv->mipi_mmio_base + 0xb898)
> +#define MIPI_CLK_LANE_TIMING(port)	 _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
> +
>  /* bits 31:0 */
>  #define _MIPIA_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb064)
>  #define _MIPIC_LP_GEN_DATA		(dev_priv->mipi_mmio_base + 0xb864)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index c98234e..03d0999 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1303,6 +1303,14 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>  		 */
>  		I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
>  
> +		if (IS_GEMINILAKE(dev_priv)) {
> +			I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
> +					intel_dsi->lp_byte_clk);
> +			/* Shadow of DPHY reg */
> +			I915_WRITE(MIPI_CLK_LANE_TIMING(port),
> +					intel_dsi->dphy_reg);
> +		}
> +
>  		/* the bw essential for transmitting 16 long packets containing
>  		 * 252 bytes meant for dcs write memory command is programmed in
>  		 * this register in terms of byte clocks. based on dsi transfer

-- 
Jani Nikula, Intel Open Source Technology Center
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