[RFC] drm/i915: Non-upstream ChromeOS patches from 3.8

[RFC] drm/i915: Non-upstream ChromeOS patches from 3.8

[james.ausmus]

Hello All-

I'm trying to determine if the ChromeOS-only patches being carried by 
Google still make sense and are the right way to do things in the 3.11+
world, and Jesse asked me to forward the patches to the list for evaluation
and potential upstreaming.

Thanks!

-James


[PATCH] drm/i915: Only apply the adaptive backlight modulation when
[PATCH] drm/i915: Add a try limit to avoid infinite loops
[PATCH] drm/i915: Add a timeout to a potentially infinite loop
[PATCH] i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7
[PATCH] drm/i915: Make intel_dp_aux_native_read timeout
[PATCH] drm/i915: Honor i915_min_freq post resume
[PATCH] Wake up DP sinks for DPCD read-based detection.
[PATCH] Restrict DP sink wake up to non-EDP.
[PATCH] Fix display underruns on Pineview with 2048x1280 VGA display.
[PATCH] CHROMIUM: drivers: i915: select non-alternate SSC frequency
[PATCH] CHROMIUM: drivers: i915: Default backlight PWM frequency
[PATCH] CHROMIUM: enable i915 power-saving render C-state 6 by
[PATCH] CHROMIUM: drm/i915: Enable LVDS downclocking
[PATCH] CHROMIUM: drm/i915: Reeneable FB compression and semaphores
[PATCH] CHROMIUM: drm/i915: Adjust the down threshold.
[PATCH] CHROMIUM: drm/i915: Adjust the RPS thresholds
[PATCH] CHROMIUM: drm/i915: Move the backlight accessor functions in
[PATCH] CHROMIUM: drm/i915: Add backlight support for Link
[PATCH] CHROMIUM: drm/i915: set enable_rc6 to per-chip default.
[PATCH] CHROMIUM: gpu: i915: optimize vblank timeout
[PATCH] CHROMIUM: i915: Allow 0 level when turning on backlight.
[PATCH] CHROMIUM: drm/i915: Check the current edp backlight state
[PATCH] CHROMIUM: drm/i915: Workaround disappearing AVI Infoframe on
[PATCH] CHROMIUM: Partial revert of
[PATCH] CHROMIUM: drm/i915: bounds check execbuffer relocations
[PATCH] CHROMIUM: drm/i915: Improve RC6p stability
[PATCH] CHROMIUM: drm/i915/intel_i2c: enable 400kHz GMBUS for
[PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for cyapa
[PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for atmel mxt bl
[PATCH] CHROMIUM: drm/i915: fix resume
[PATCH] CHROMIUM: drm/i915: Fix warning
[PATCH] CHROMIUM: drm/i915: Initialize the backlight when reported
[PATCH] CHROMIUM: drm/i915: Don't evict bound object in the shrinker
[PATCH] CHROMIUM: drm/i915/intel_drv: reduce wait_for polling time
[PATCH] CHROMIUM: drm/i915: tune the RC6 timeout for stability
[PATCH] CHROMIUM: drm/i915: repin bound framebuffers on resume
[PATCH] CHROMIUM: i915: fix max backlight in normal mode
[PATCH] CHROMIUM: drm/i915: Tune the rc6 value again
[PATCH] CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays
[PATCH] CHROMIUM: drm/i915: set lower RC6_THRESHOLD for HSW
[PATCH] CHROMIUM: drm/i915: set linetime WM based on target_clock
[PATCH] CHROMIUM: drivers: i915: intel_hdmi deleted unused variable
[PATCH] CHROMIUM: drm/i915: Increase the wakeup up delay for PPT
[PATCH] CHROMIUM: drm/i915: Don't load boot context at init time on

[PATCH] drm/i915: Only apply the adaptive backlight modulation when it is enabled.

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

Otherwise things go very, very dark.

BUG=chromium-os:33854
TEST=by hand

Change-Id: I3122447a255652ba5c98863664c0f60e1859c490
Reviewed-on: https://gerrit.chromium.org/gerrit/31293
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
[marcheu: fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_panel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index cebabb0..92678f6 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -289,6 +289,9 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 tmp;
 
+	if (dev_priv->adaptive_backlight_enabled)
+		level = level * dev_priv->backlight_correction_level >> 8;
+
 	DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
 	level = intel_panel_compute_brightness(dev, level);
 
-- 
1.8.3.2

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[PATCH] drm/i915: Add a try limit to avoid infinite loops

[james.ausmus]

From: Chris Wolfe <cwolfe@chromium.org>

Unfortunately some combinations of hardware seem to generate successful
communications on the aux channel, which always report deferred. As a
result native_write can wind up in an infinite loop.

This hack adds a large (~10ms) retry limit to avoid a kernel panic,
while hopefully minimizing the impact on working hardware.

Signed-off-by: cwolfe@chromium.org

BUG=chromium-os:34840
TEST=Manually connect DP to VGA adapter to problem system. Added display
     powers up and works normally, rather than black screen and reboot.

Change-Id: Ib1b0001ca8004e65c9c5e353dbdb5e252fd88438
Reviewed-on: https://gerrit.chromium.org/gerrit/34203
Commit-Ready: Chris Wolfe <cwolfe@chromium.org>
Reviewed-by: Chris Wolfe <cwolfe@chromium.org>
Tested-by: Chris Wolfe <cwolfe@chromium.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e5d16bc..ac7d610 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -491,6 +491,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
 	uint8_t	msg[20];
 	int msg_bytes;
 	uint8_t	ack;
+	int try;
 
 	intel_dp_check_edp(intel_dp);
 	if (send_bytes > 16)
@@ -501,7 +502,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
 	msg[3] = send_bytes - 1;
 	memcpy(&msg[4], send, send_bytes);
 	msg_bytes = send_bytes + 4;
-	for (;;) {
+	for (try = 0; try < 100; try++) {
 		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 		if (ret < 0)
 			return ret;
@@ -512,6 +513,10 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
 		else
 			return -EIO;
 	}
+	if (try == 100) {
+		DRM_ERROR("too many retries, giving up\n");
+		return -EREMOTEIO;
+	}
 	return send_bytes;
 }
 
-- 
1.8.3.2

[PATCH] drm/i915: Add a timeout to a potentially infinite loop

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

BUG=chromium:148595
TEST=by hand, connect a mac DP to VGA adapter, machine doesn't reboot.

Change-Id: I29d518a7e2d906291d75da58a0d4a7c6296658cc
Reviewed-on: https://gerrit.chromium.org/gerrit/33489
Reviewed-by: Mandeep Singh Baines <msb@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Stuart Abercrombie <sabercrombie@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
[marcheu: fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ac7d610..29013de 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -345,7 +345,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 	int recv_bytes;
 	uint32_t status;
 	uint32_t aux_clock_divider;
-	int try, precharge;
+	int try, aux_ch_try, precharge;
 
 	if (IS_HASWELL(dev)) {
 		switch (intel_dig_port->port) {
@@ -428,7 +428,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 			   DP_AUX_CH_CTL_DONE |
 			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
 			   DP_AUX_CH_CTL_RECEIVE_ERROR);
-		for (;;) {
+		/* Wait 1 ms then timeout, it should be sufficient since the
+		 * timeout above is 400us
+		 */
+		for (aux_ch_try = 0; aux_ch_try < 10; aux_ch_try++) {
 			status = I915_READ(ch_ctl);
 			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 				break;
@@ -448,6 +451,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 		if (status & DP_AUX_CH_CTL_DONE)
 			break;
 	}
+	/* If after 5 tries we're still busy, give up. */
+	if ((status & DP_AUX_CH_CTL_SEND_BUSY) != 0)
+		return -EIO;
 
 	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
-- 
1.8.3.2

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[PATCH] i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7

[james.ausmus]

From: Duncan Laurie <dlaurie@chromium.org>

We had been using a DMI table workaround to select the right
frequency for devices, but this is fragile and must be updated
with every new platform.

Instead the default case when VBT is missing is changed to use
120MHz clock for LVDS SSC for these generations.

The docs for 2010-Core, SandyBridge, and IvyBridge all indicate
that the reference frequency for LVDS is 120MHz:

"2010 Core"
http://intellinuxgraphics.org/IHD_OS_Vol3_Part3r2.pdf
page 38
Reference Frequency: 120MHz for CRT and LVDS.  100MHz for the FDI.

"2011 SandyBridge"
http://intellinuxgraphics.org/documentation/SNB/IHD_OS_Vol3_Part3.pdf
page 33
Reference Frequency: 120MHz for CRT, HDMI, LVDS.  100MHz for the FDI.

"2012 IvyBridge"
http://intellinuxgraphics.org/documentation/IVB/IHD_OS_Vol3_Part4.pdf
page 27
Reference Frequency: 120 MHz for CRT, HDMI, LVDS, 100MHz for the FDI.

BUG=chrome-os-partner:11744
TEST=manual: boot on Lumpy and Parrot with and without VBIOS

Change-Id: Ieae3d37d4a5f6eb11c45a5e2fa76b0c106404e69
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/28274
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
[marcheu: fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_bios.c | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index b6a8b69..7aa5fc1 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -631,17 +631,6 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
 	return;
 }
 
-static const struct dmi_system_id lvds_do_not_use_alternate_frequency[] = {
-	{
-		.callback = NULL,
-		.ident = "Lumpy",
-		.matches = {
-			DMI_MATCH(DMI_PRODUCT_NAME, "Lumpy"),
-		}
-	},
-	{ }
-};
-
 static void
 init_vbt_defaults(struct drm_i915_private *dev_priv)
 {
@@ -662,7 +651,9 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 
 	/* Default to using SSC */
 	dev_priv->lvds_use_ssc = 1;
-	if (dmi_check_system(lvds_do_not_use_alternate_frequency))
+
+	/* Core/SandyBridge/IvyBridge use 120MHz reference clock for LVDS */
+	if (HAS_PCH_SPLIT(dev))
 		dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 0);
 	else
 		dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
-- 
1.8.3.2

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[PATCH] drm/i915: Make intel_dp_aux_native_read timeout

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

Some adapters return DEFER indefinitely, which results in being stuck in the
kernel, which triggers the watchdog, which reboots. To avoid this, limit to
100 tries, after which we return an error and pring a message.

BUG=chrome-os-partner:15612
TEST=by hand, use the apple miniDP to dual-link adapter, plug a 30 inch
TEST=monitor, the machine shouldn't reboot spontaneously (the monitor still
TEST=won't work, but that is a separate bug).

Change-Id: I842f6edd0da3b67eab8613410bf61474fc40ba7a
Reviewed-on: https://gerrit.chromium.org/gerrit/39888
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Stuart Abercrombie <sabercrombie@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f763d45..c271c05 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -545,6 +545,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
 	int reply_bytes;
 	uint8_t ack;
 	int ret;
+	int try;
 
 	intel_dp_check_edp(intel_dp);
 	msg[0] = AUX_NATIVE_READ << 4;
@@ -555,7 +556,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
 	msg_bytes = 4;
 	reply_bytes = recv_bytes + 1;
 
-	for (;;) {
+	for (try = 0; try < 100; try++) {
 		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 				      reply, reply_bytes);
 		if (ret == 0)
@@ -572,6 +573,9 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
 		else
 			return -EIO;
 	}
+
+	DRM_ERROR("too many retries, giving up\n");
+	return -EREMOTEIO;
 }
 
 static int
-- 
1.8.3.2

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[PATCH] drm/i915: Honor i915_min_freq post resume

[james.ausmus]

From: Sameer Nanda <snanda@chromium.org>

The i915_min_freq setting was not getting honored on the resume path.
Fixed it.

BUG=chrome-os-partner:16439
TEST="cat /sys/kernel/debug/dri/0/i915_min_freq" and remember the value
returned. Do a suspend/resume cycle. cat the i915_min_freq file again,
it must return the same value as read earlier.

Change-Id: Ie3cc8e8794a59c154b511e24e468daef94a44765
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/41461
[marcheu: fixup for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9ff2285..7e1c629 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -30,6 +30,7 @@
 #include "intel_drv.h"
 #include "../../../platform/x86/intel_ips.h"
 #include <linux/module.h>
+#include <linux/kernel.h>
 
 #define FORCEWAKE_ACK_TIMEOUT_MS 2
 
@@ -2637,7 +2638,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
 	}
 
-	gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
+	gen6_set_rps(dev_priv->dev, (u8)max((gt_perf_status & 0xff00) >> 8, 10u));
 
 	/* requires MSI enabled */
 	I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
-- 
1.8.3.2

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[PATCH] Wake up DP sinks for DPCD read-based detection.

[james.ausmus]

From: Stuart Abercrombie <sabercrombie@chromium.org>

When in DPMS sleep state the Apple mini DP->VGA adapter doesn't respond.
This led to no external display on boot.

v2: Avoid DPCD check and keep AUX awake for EDID read.

BUG=chrome-os-partner:17063
TEST=Straight DP and various adapters on mini-DP and DP platforms.

Change-Id: I90bea73006ae9c99464b0b5bc57f3803918313a8
Reviewed-on: https://gerrit.chromium.org/gerrit/42583
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Commit-Queue: Stuart Abercrombie <sabercrombie@chromium.org>
Tested-by: Stuart Abercrombie <sabercrombie@chromium.org>
[marcheu: fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 32 ++++++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c271c05..f886ae9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1290,14 +1290,10 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
 }
 
 /* If the sink supports it, try to set the power state appropriately */
-void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
+static void intel_dp_do_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
 	int ret, i;
 
-	/* Should have a valid DPCD by this point */
-	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
-		return;
-
 	if (mode != DRM_MODE_DPMS_ON) {
 		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
 						  DP_SET_POWER_D3);
@@ -1319,6 +1315,16 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 	}
 }
 
+/* If we have a valid DPCD, set the power state. */
+void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
+{
+	/* Should have a valid DPCD by this point */
+	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
+		return;
+
+	intel_dp_do_sink_dpms(intel_dp, mode);
+}
+
 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 				  enum pipe *pipe)
 {
@@ -2330,6 +2336,12 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 
 	intel_dp->has_audio = false;
 
+	/* Ensure the sink is awake for DPCD/EDID reads. */
+	if (connector->dpms != DRM_MODE_DPMS_ON) {
+		/* Bypass DPCD check, since we obtain it during detection. */
+		intel_dp_do_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	}
+
 	if (HAS_PCH_SPLIT(dev))
 		status = ironlake_dp_detect(intel_dp);
 	else
@@ -2339,8 +2351,11 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
 	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
 
-	if (status != connector_status_connected)
+	if (status != connector_status_connected) {
+		if (connector->dpms != DRM_MODE_DPMS_ON)
+			intel_dp_do_sink_dpms(intel_dp, connector->dpms);
 		return status;
+	}
 
 	intel_dp_probe_oui(intel_dp);
 
@@ -2356,6 +2371,11 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 
 	if (intel_encoder->type != INTEL_OUTPUT_EDP)
 		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+
+	/* Restore the sink state */
+	if (connector->dpms != DRM_MODE_DPMS_ON)
+		intel_dp_do_sink_dpms(intel_dp, connector->dpms);
+
 	return connector_status_connected;
 }
 
-- 
1.8.3.2

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[PATCH] Restrict DP sink wake up to non-EDP.

[james.ausmus]

From: Stuart Abercrombie <sabercrombie@chromium.org>

Doing it on EDP was producing a kernel warning with screen power down.

BUG=chrome-os-partner:17893
TEST=No warning with screen power down.  Apple mini DP->VGA adapter still works.

Change-Id: I769c31b43753c7ced7cb0b2f0d50fc96c2486779
[sonnyrao: 3.8: fixup for 3.8]
Reviewed-on: https://gerrit.chromium.org/gerrit/45814
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Commit-Queue: Stuart Abercrombie <sabercrombie@chromium.org>
Tested-by: Stuart Abercrombie <sabercrombie@chromium.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f886ae9..d896cb8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2337,7 +2337,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 	intel_dp->has_audio = false;
 
 	/* Ensure the sink is awake for DPCD/EDID reads. */
-	if (connector->dpms != DRM_MODE_DPMS_ON) {
+	if (!is_edp(intel_dp) && connector->dpms != DRM_MODE_DPMS_ON) {
 		/* Bypass DPCD check, since we obtain it during detection. */
 		intel_dp_do_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	}
@@ -2352,7 +2352,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
 
 	if (status != connector_status_connected) {
-		if (connector->dpms != DRM_MODE_DPMS_ON)
+		if (!is_edp(intel_dp) && connector->dpms != DRM_MODE_DPMS_ON)
 			intel_dp_do_sink_dpms(intel_dp, connector->dpms);
 		return status;
 	}
@@ -2373,7 +2373,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
 
 	/* Restore the sink state */
-	if (connector->dpms != DRM_MODE_DPMS_ON)
+	if (!is_edp(intel_dp) && connector->dpms != DRM_MODE_DPMS_ON)
 		intel_dp_do_sink_dpms(intel_dp, connector->dpms);
 
 	return connector_status_connected;
-- 
1.8.3.2

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[PATCH] Fix display underruns on Pineview with 2048x1280 VGA display.

[james.ausmus]

From: Stuart Abercrombie <sabercrombie@chromium.org>

Higher dot clocks were working because pixel doubling was enabled.

Lower the apparently arbitrary threshold so it's enabled for 2048x1280.

Intel hasn't felt moved to document any of this, so this is purely empirical.

The original threshold was introduced here:
http://cgit.freedesktop.org/~anholt/xf86-video-intel/commit/?id=8fcf9a81179ee8577ddab5e904c58fbfd14cf59c

Change-Id: I1eff5db3f26fc2e7953edae9422047353f66f475
Reviewed-on: https://gerrit.chromium.org/gerrit/49896
Tested-by: Stuart Abercrombie <sabercrombie@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Commit-Queue: Stuart Abercrombie <sabercrombie@chromium.org>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7bd1d7a..349f019 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4805,14 +4805,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		dspcntr |= DISPPLANE_SEL_PIPE_B;
 
 	if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
-		/* Enable pixel doubling when the dot clock is > 90% of the (display)
+		/* Enable pixel doubling when the dot clock is > 85% of the (display)
 		 * core speed.
 		 *
 		 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
 		 * pipe == 0 check?
 		 */
 		if (mode->clock >
-		    dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
+		    dev_priv->display.get_display_clock_speed(dev) * 17 / 20)
 			pipeconf |= PIPECONF_DOUBLE_WIDE;
 		else
 			pipeconf &= ~PIPECONF_DOUBLE_WIDE;
-- 
1.8.3.2

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[PATCH] CHROMIUM: drivers: i915: select non-alternate SSC frequency for some systems

[james.ausmus]

From: Simon Que <sque@chromium.org>

When initializing VBT default values, the alternate BIOS SSC frequency
is selected.  This patch allows the non-alternate frequency to be
selected as a default, for specified systems.  There is a DMI match list
for systems that are to use the non-alternate frequency.  Currently,
only Lumpy is on the list.

BUG=chrome-os-partner:5525
TEST=Run on Lumpy with dev switch off.  The display should be working,
even if the backlight is not -- something should be visible.

Change-Id: I6c5c57ab38cfb21731a6d56b143c7906b8c85360
Signed-off-by: Simon Que <sque@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11339
Reviewed-by: Bryan Freed <bfreed@chromium.org>
[marcheu: fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_bios.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 55ffba1..b6a8b69 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -631,6 +631,17 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
 	return;
 }
 
+static const struct dmi_system_id lvds_do_not_use_alternate_frequency[] = {
+	{
+		.callback = NULL,
+		.ident = "Lumpy",
+		.matches = {
+			DMI_MATCH(DMI_PRODUCT_NAME, "Lumpy"),
+		}
+	},
+	{ }
+};
+
 static void
 init_vbt_defaults(struct drm_i915_private *dev_priv)
 {
@@ -651,7 +662,10 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 
 	/* Default to using SSC */
 	dev_priv->lvds_use_ssc = 1;
-	dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+	if (dmi_check_system(lvds_do_not_use_alternate_frequency))
+		dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 0);
+	else
+		dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
 	DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
 }
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drivers: i915: Default backlight PWM frequency

[james.ausmus]

From: Simon Que <sque@chromium.org>

If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz.  This is determined using the following
formula:

  freq = refclk / (128 * pwm_max)

The PWM register allows the max PWM value to be set.  So we want to use
the formula, where freq = 200:

  pwm_max = refclk / (128 * freq)

This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency.  Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.

If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.

BUG=chrome-os-partner:5570
TEST=x86 backlight works smoothly w/o dev mode

Change-Id: I4219ab8a2481afbcc3586288594b066fcc6c8294
Signed-off-by: Simon Que <sque@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/11629
Reviewed-by: Bryan Freed <bfreed@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
[marcheu: Fixed up for dev_priv->dev and regfile transition]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_panel.c | 39 ++++++++++++++++++++++++++++++++------
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index bee8cb6..affd930 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -35,6 +35,12 @@
 
 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
 
+/* These are used to calculate a reasonable default when firmware has not
+ * configured a maximum PWM frequency, with 200Hz as the current default target.
+ */
+#define DEFAULT_BACKLIGHT_PWM_FREQ   200
+#define BACKLIGHT_REFCLK_DIVISOR     128
+
 void
 intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
 		       struct drm_display_mode *adjusted_mode)
@@ -130,13 +136,34 @@ static int is_backlight_combination_mode(struct drm_device *dev)
 	return 0;
 }
 
+static void i915_set_default_max_backlight(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 refclk_freq_mhz = 0;
+	u32 max_pwm;
+
+	if (HAS_PCH_SPLIT(dev_priv->dev))
+		refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+	else if (dev_priv->lvds_use_ssc)
+		refclk_freq_mhz = dev_priv->lvds_ssc_freq;
+
+	max_pwm = refclk_freq_mhz * 1000000 /
+			(BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+	if (HAS_PCH_SPLIT(dev_priv->dev))
+		dev_priv->regfile.saveBLC_PWM_CTL2 = max_pwm << 16;
+	else if (IS_PINEVIEW(dev_priv->dev))
+		dev_priv->regfile.saveBLC_PWM_CTL = max_pwm << 17;
+	else
+		dev_priv->regfile.saveBLC_PWM_CTL = max_pwm << 16;
+}
+
 static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val;
 
-	/* Restore the CTL value if it lost, e.g. GPU reset */
-
+	/* Restore the CTL value if it was lost, e.g. GPU reset */
 	if (HAS_PCH_SPLIT(dev_priv->dev)) {
 		val = I915_READ(BLC_PWM_PCH_CTL2);
 		if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
@@ -191,11 +218,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
 
 	max = _intel_panel_get_max_backlight(dev);
 	if (max == 0) {
-		/* XXX add code here to query mode clock or hardware clock
-		 * and program max PWM appropriately.
+		/* If backlight PWM registers have not been set, set them to
+		 * default backlight PWM settings.
 		 */
-		pr_warn_once("fixme: max PWM is zero\n");
-		return 1;
+		i915_set_default_max_backlight(dev);
+		max = i915_read_blc_pwm_ctl(dev);
 	}
 
 	DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
-- 
1.8.3.2

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[PATCH] CHROMIUM: enable i915 power-saving render C-state 6 by default.

[james.ausmus]

From: Todd Broch <tbroch@chromium.org>

BUG=chrome-os-partner:6768
TEST=manual,
- boot kernel
1. cat /sys/module/i915/parameters/i915_enable_rc6
  - should equal 1
2. start powertop, goto 'Idle Stats' tab
  - make sure that the Package c-states (C6, C7) are entered at some
    non-trivial percentage when system is idle

Signed-off-by: Todd Broch <tbroch@chromium.org>
Change-Id: Ib557a14e3cf20b55a6670808e681ef21b1e0ed1b
Reviewed-on: https://gerrit.chromium.org/gerrit/12280
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1172658..cdcc7c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -63,8 +63,8 @@ module_param_named(semaphores, i915_semaphores, int, 0600);
 MODULE_PARM_DESC(semaphores,
 		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
 
-int i915_enable_rc6 __read_mostly = -1;
-module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
+int i915_enable_rc6 __read_mostly = 1;
+module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 MODULE_PARM_DESC(i915_enable_rc6,
 		"Enable power-saving render C-state 6. "
 		"Different stages can be selected via bitmask values "
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Enable LVDS downclocking

[james.ausmus]

From: Sean Paul <seanpaul@chromium.org>

Enable LVDS downclocking in the intel i915 graphics driver. This
will save approximately 200mW when the screen is idle.

Signed-off-by: Sean Paul <seanpaul@chromium.org>

BUG=chromium-os:9803
TEST=Tested on alex and lumpy

Change-Id: I6fe403c8d9d520901a01549ad6b5eff80de318f3
Reviewed-on: https://gerrit.chromium.org/gerrit/14815
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Commit-Ready: Sean Paul <seanpaul@chromium.org>
Tested-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cdcc7c0..5351f58 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -78,7 +78,7 @@ MODULE_PARM_DESC(i915_enable_fbc,
 		"Enable frame buffer compression for power savings "
 		"(default: -1 (use per-chip default))");
 
-unsigned int i915_lvds_downclock __read_mostly = 0;
+unsigned int i915_lvds_downclock __read_mostly = 1;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 MODULE_PARM_DESC(lvds_downclock,
 		"Use panel (LVDS/eDP) downclocking for power savings "
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Reeneable FB compression and semaphores for kernel 3.2

[james.ausmus]

From: Simon Que <sque@chromium.org>

marcheu added these changes in kernel 3.0:
 https://gerrit.chromium.org/gerrit/12367
 https://gerrit.chromium.org/gerrit/12368

They were undone in kernel 3.2.  This patch restores them.

BUG=chromium-os:27468
TEST=power_x86Settings autotest passes with kernel 3.2

Change-Id: Ic5a104eb73697cfa9a437ae2c4868051a77ad91f
Signed-off-by: Simon Que <sque@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/18687
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5351f58..4c4cfdb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -58,10 +58,10 @@ module_param_named(powersave, i915_powersave, int, 0600);
 MODULE_PARM_DESC(powersave,
 		"Enable powersavings, fbc, downclocking, etc. (default: true)");
 
-int i915_semaphores __read_mostly = -1;
+int i915_semaphores __read_mostly = 1;
 module_param_named(semaphores, i915_semaphores, int, 0600);
 MODULE_PARM_DESC(semaphores,
-		"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
+		"Use semaphores for inter-ring sync (default: true)");
 
 int i915_enable_rc6 __read_mostly = 1;
 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
@@ -72,11 +72,11 @@ MODULE_PARM_DESC(i915_enable_rc6,
 		"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
 		"default: -1 (use per-chip default)");
 
-int i915_enable_fbc __read_mostly = -1;
+int i915_enable_fbc __read_mostly = 1;
 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
 MODULE_PARM_DESC(i915_enable_fbc,
 		"Enable frame buffer compression for power savings "
-		"(default: -1 (use per-chip default))");
+		"(default: true)");
 
 unsigned int i915_lvds_downclock __read_mostly = 1;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Adjust the down threshold.

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

The thresholds for GPU reclocking are highly asymetrical. This creates an
interesting phenomenon on Chrome startup where the clock ramps up very
quickly, and then the blinking cursor is enough to keep it up. Obviously
having the max GPU clock on the login screen is very bad for thermals.

With this change, the clock goes back to its minimum frequency after a couple
of seconds.

BUG=chrome-os-partner:11009
TEST=checked that a blinking cursor lets the GPU clock go back to 350Mhz

Change-Id: I3b8de74864907abdb3c7c4aeb0ab4fcf2eaf0b2c
Reviewed-on: https://gerrit.chromium.org/gerrit/26641
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
[marcheu: Fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3280cff..6d5e3ed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2612,7 +2612,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 		   dev_priv->rps.min_delay << 16);
 
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
 	I915_WRITE(GEN6_RP_UP_EI, 66000);
 	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Adjust the RPS thresholds

[james.ausmus]

From: Sean Paul <seanpaul@chromium.org>

Lower the RPS thresholds and make them symmetric. This patch increases
the rate of change of the GPU clock, allowing it to clock up more
quickly, and more importantly, clock down when necessary. The problem
this patch solves is that a heavy workload would inflate the clock, and
then the clock would stick high when the workload went away because the
down threshold was too high. This should improve our thermals and power.

BUG=chrome-os-partner:11009
TEST=Tested with the PBS koala video, play it along with a GL demo to
get the clock up to 1150MHz. Remove the GL demo workload and ensure the
clock goes back down to 350MHz.

Change-Id: I9a489ffd4810fb2b3c2544d6165d664899ec0e54
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27184
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
[marcheu: Fixups for 3.8]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6d5e3ed..9ff2285 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2611,8 +2611,8 @@ static void gen6_enable_rps(struct drm_device *dev)
 		   dev_priv->rps.max_delay << 24 |
 		   dev_priv->rps.min_delay << 16);
 
-	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0x4000);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x4000);
 	I915_WRITE(GEN6_RP_UP_EI, 66000);
 	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Move the backlight accessor functions in dev_priv

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

This abstracts those functions, so that we can plug-in
platform-specific alternatives.

BUG=chrome-os-partner:3276,chrome-os-partner:15248
TEST=by hand: compiles, works

Change-Id: I29dd15722ffed8f5813b34bf0ce4431ce0524cc2
Reviewed-on: https://gerrit.chromium.org/gerrit/36974
Reviewed-by: Daniel Erat <derat@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
[marcheu: fixup for 3.8 rebase]
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.h    |  8 +++++++-
 drivers/gpu/drm/i915/intel_dp.c    |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h   |  3 ---
 drivers/gpu/drm/i915/intel_lvds.c  |  4 ++--
 drivers/gpu/drm/i915/intel_modes.c |  1 +
 drivers/gpu/drm/i915/intel_panel.c | 25 +++++++++++++++++--------
 6 files changed, 29 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12ab3bd..67932ce 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -704,6 +704,13 @@ typedef struct drm_i915_private {
 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 
+	/* Backlight driver */
+	u32 (*get_backlight)(struct drm_device *dev);
+	u32 (*get_max_backlight)(struct drm_device *dev);
+	void (*set_backlight)(struct drm_device *dev, u32 level);
+	void (*disable_backlight)(struct drm_device *dev);
+	void (*enable_backlight)(struct drm_device *dev, enum pipe pipe);
+
 	/* Feature bits from the VBIOS */
 	unsigned int int_tv_support:1;
 	unsigned int lvds_dither:1;
@@ -915,7 +922,6 @@ typedef struct drm_i915_private {
 
 	struct drm_property *broadcast_rgb_property;
 	struct drm_property *force_audio_property;
-
 	bool hw_contexts_disabled;
 	uint32_t hw_context_size;
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fb3715b..d5f3105 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1196,7 +1196,7 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	I915_WRITE(PCH_PP_CONTROL, pp);
 	POSTING_READ(PCH_PP_CONTROL);
 
-	intel_panel_enable_backlight(dev, pipe);
+	dev_priv->enable_backlight(dev, pipe);
 }
 
 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
@@ -1208,7 +1208,7 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 	if (!is_edp(intel_dp))
 		return;
 
-	intel_panel_disable_backlight(dev);
+	dev_priv->disable_backlight(dev);
 
 	DRM_DEBUG_KMS("\n");
 	pp = ironlake_get_pp_control(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8a1bd4a..4f41b8a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -488,9 +488,6 @@ extern void intel_pch_panel_fitting(struct drm_device *dev,
 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
 extern int intel_panel_setup_backlight(struct drm_connector *connector);
-extern void intel_panel_enable_backlight(struct drm_device *dev,
-					 enum pipe pipe);
-extern void intel_panel_disable_backlight(struct drm_device *dev);
 extern void intel_panel_destroy_backlight(struct drm_device *dev);
 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 17aee74..a2b9450 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -136,7 +136,7 @@ static void intel_enable_lvds(struct intel_encoder *encoder)
 	if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
 		DRM_ERROR("timed out waiting for panel to power on\n");
 
-	intel_panel_enable_backlight(dev, intel_crtc->pipe);
+	dev_priv->enable_backlight(dev, intel_crtc->pipe);
 }
 
 static void intel_disable_lvds(struct intel_encoder *encoder)
@@ -156,7 +156,7 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
 		stat_reg = PP_STATUS;
 	}
 
-	intel_panel_disable_backlight(dev);
+	dev_priv->disable_backlight(dev);
 
 	I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
 	if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index b00f1c8..0d9b115 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -126,3 +126,4 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
 
 	drm_object_attach_property(&connector->base, prop, 0);
 }
+
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index affd930..dddd4a1 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,7 @@
 
 #include <linux/moduleparam.h>
 #include "intel_drv.h"
+#include "i915_drv.h"
 
 #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
 
@@ -245,7 +246,7 @@ static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
 
 	if (i915_panel_invert_brightness > 0 ||
 	    dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS)
-		return intel_panel_get_max_backlight(dev) - val;
+		return dev_priv->get_max_backlight(dev) - val;
 
 	return val;
 }
@@ -294,7 +295,7 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level
 		return intel_pch_panel_set_backlight(dev, level);
 
 	if (is_backlight_combination_mode(dev)) {
-		u32 max = intel_panel_get_max_backlight(dev);
+		u32 max = dev_priv->get_max_backlight(dev);
 		u8 lbpc;
 
 		lbpc = level * 0xfe / max + 1;
@@ -318,7 +319,7 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level)
 		intel_panel_actually_set_backlight(dev, level);
 }
 
-void intel_panel_disable_backlight(struct drm_device *dev)
+static void intel_panel_disable_backlight(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
@@ -340,13 +341,13 @@ void intel_panel_disable_backlight(struct drm_device *dev)
 	}
 }
 
-void intel_panel_enable_backlight(struct drm_device *dev,
-				  enum pipe pipe)
+static void intel_panel_enable_backlight(struct drm_device *dev,
+					 enum pipe pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if (dev_priv->backlight_level == 0)
-		dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
+		dev_priv->backlight_level = dev_priv->get_max_backlight(dev);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		uint32_t reg, tmp;
@@ -395,7 +396,13 @@ static void intel_panel_init_backlight(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	dev_priv->backlight_level = intel_panel_get_backlight(dev);
+	dev_priv->get_backlight = intel_panel_get_backlight;
+	dev_priv->get_max_backlight = intel_panel_get_max_backlight;
+	dev_priv->set_backlight = intel_panel_set_backlight;
+	dev_priv->disable_backlight = intel_panel_disable_backlight;
+	dev_priv->enable_backlight = intel_panel_enable_backlight;
+
+	dev_priv->backlight_level = dev_priv->get_backlight(dev);
 	dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
 }
 
@@ -425,7 +432,9 @@ intel_panel_detect(struct drm_device *dev)
 static int intel_panel_update_status(struct backlight_device *bd)
 {
 	struct drm_device *dev = bl_get_data(bd);
-	intel_panel_set_backlight(dev, bd->props.brightness);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->set_backlight(dev, bd->props.brightness);
 	return 0;
 }
 
-- 
1.8.3.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] CHROMIUM: drm/i915: Add backlight support for Link

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

This adds device-specific backlight support for Link, and also
enables adaptive backlight by default there.

BUG=chrome-os-partner:13276,chrome-os-partner:15248
TEST=by hand

Change-Id: I9ef546bba9f121657a653aa9cfc6a80bbde55cb0
Reviewed-on: https://gerrit.chromium.org/gerrit/36976
Reviewed-by: Daniel Erat <derat@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
[marcheu: Fixups for 3.8]
---
 drivers/gpu/drm/i915/Makefile                   |   1 +
 drivers/gpu/drm/i915/i915_drv.h                 |  17 +
 drivers/gpu/drm/i915/i915_irq.c                 |   4 +-
 drivers/gpu/drm/i915/i915_reg.h                 |  22 ++
 drivers/gpu/drm/i915/intel_adaptive_backlight.c | 401 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c                 |  24 ++
 drivers/gpu/drm/i915/intel_drv.h                |   3 +
 drivers/gpu/drm/i915/intel_fixedpoint.h         | 143 +++++++++
 drivers/gpu/drm/i915/intel_modes.c              |  48 +++
 drivers/gpu/drm/i915/intel_panel.c              |  38 +++
 10 files changed, 700 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/intel_adaptive_backlight.c
 create mode 100644 drivers/gpu/drm/i915/intel_fixedpoint.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0f2c549..1c8613d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -16,6 +16,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
 	  i915_gem_tiling.o \
 	  i915_sysfs.o \
 	  i915_trace_points.o \
+	  intel_adaptive_backlight.o \
 	  intel_display.o \
 	  intel_crt.o \
 	  intel_lvds.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 67932ce..646c3eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -711,6 +711,13 @@ typedef struct drm_i915_private {
 	void (*disable_backlight)(struct drm_device *dev);
 	void (*enable_backlight)(struct drm_device *dev, enum pipe pipe);
 
+	/* Adaptive backlight */
+	bool adaptive_backlight_enabled;
+	int backlight_correction_level;
+	int backlight_correction_count;
+	int backlight_correction_direction;
+	int adaptive_backlight_panel_gamma; /* as 16.16 fixed point */
+
 	/* Feature bits from the VBIOS */
 	unsigned int int_tv_support:1;
 	unsigned int lvds_dither:1;
@@ -922,6 +929,9 @@ typedef struct drm_i915_private {
 
 	struct drm_property *broadcast_rgb_property;
 	struct drm_property *force_audio_property;
+	struct drm_property *adaptive_backlight_property;
+	struct drm_property *panel_gamma_property;
+
 	bool hw_contexts_disabled;
 	uint32_t hw_context_size;
 
@@ -1627,6 +1637,13 @@ extern int i915_restore_state(struct drm_device *dev);
 void i915_setup_sysfs(struct drm_device *dev_priv);
 void i915_teardown_sysfs(struct drm_device *dev_priv);
 
+/* intel_adaptive_backlight.c */
+extern void intel_adaptive_backlight(struct drm_device *dev, int pipe);
+extern void intel_adaptive_backlight_enable(struct drm_i915_private *dev_priv);
+extern void intel_adaptive_backlight_disable(struct drm_i915_private *dev_priv,
+					     struct drm_connector *connector);
+extern void intel_adaptive_backlight_setup(struct drm_device *dev);
+
 /* intel_i2c.c */
 extern int intel_setup_gmbus(struct drm_device *dev);
 extern void intel_teardown_gmbus(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fe84338..17f6406 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -707,8 +707,10 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 			intel_opregion_gse_intr(dev);
 
 		for (i = 0; i < 3; i++) {
-			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
+			if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) {
 				drm_handle_vblank(dev, i);
+				intel_adaptive_backlight(dev, i);
+			}
 			if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 				intel_prepare_page_flip(dev, i);
 				intel_finish_page_flip_plane(dev, i);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 59afb7e..157cb5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1960,6 +1960,28 @@
 #define BLC_PWM_CPU_CTL2	0x48250
 #define BLC_PWM_CPU_CTL		0x48254
 
+#define BLM_HIST_CTL			0x48260
+#define  ENH_HIST_ENABLE		(1<<31)
+#define  ENH_MODIF_TBL_ENABLE		(1<<30)
+#define  ENH_PIPE_A_SELECT		(0<<29)
+#define  ENH_PIPE_B_SELECT		(1<<29)
+#define  ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
+#define  HIST_MODE_YUV			(0<<24)
+#define  HIST_MODE_HSV			(1<<24)
+#define  ENH_MODE_DIRECT		(0<<13)
+#define  ENH_MODE_ADDITIVE		(1<<13)
+#define  ENH_MODE_MULTIPLICATIVE	(2<<13)
+#define  BIN_REGISTER_SET		(1<<11)
+#define  ENH_NUM_BINS			32
+
+#define BLM_HIST_ENH			0x48264
+
+#define BLM_HIST_GUARD_BAND		0x48268
+#define  BLM_HIST_INTR_ENABLE		(1<<31)
+#define  BLM_HIST_EVENT_STATUS		(1<<30)
+#define  BLM_HIST_INTR_DELAY_MASK	(0xFF<<22)
+#define  BLM_HIST_INTR_DELAY_SHIFT	22
+
 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
 #define BLC_PWM_PCH_CTL1	0xc8250
diff --git a/drivers/gpu/drm/i915/intel_adaptive_backlight.c b/drivers/gpu/drm/i915/intel_adaptive_backlight.c
new file mode 100644
index 0000000..aa610c3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_adaptive_backlight.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) 2012 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include "drmP.h"
+#include "i915_drm.h"
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_drv.h"
+#include "intel_fixedpoint.h"
+
+/*
+ * Some notes about the adaptive backlight implementation:
+ * - If we let it run as designed, it will generate a lot of interrupts which
+ *   tends to wake the CPU up and waste power. This is a bad idea for a power
+ *   saving feature. Instead, we couple it to the vblank interrupt since that
+ *   means we drew something. This means that we do not react to non-vsynced
+ *   GL updates, or updates to the front buffer, and also adds a little bit of
+ *   extra latency. But it is an acceptable tradeoff to make.
+ * - Ivy bridge has a hardware issue where the color correction doesn't seem
+ *   to work. When you enable the ENH_MODIF_TBL_ENABLE bit, not only does the
+ *   correction not work, but it becomes impossible to read the levels.
+ *   Instead, as a workaround, we don't set that bit on ivy bridge and
+ *   (ab)use the gamma ramp registers to do the correction.
+ */
+
+/*
+ * This function takes a histogram of buckets as input and determines an
+ * acceptable target backlight level.
+ */
+static int histogram_find_correction_level(int *levels)
+{
+	int i, sum = 0;
+	int ratio, distortion, prev_distortion = 0, off, final_ratio, target;
+
+	for (i = 0; i < ENH_NUM_BINS; i++)
+		sum += levels[i];
+
+	/* Allow 0.33/256 distortion per pixel, on average */
+	target = sum / 3;
+
+	/* Special case where we only have less than 100 pixels
+	 * outside of the darkest bin.
+	 */
+	if (sum - levels[0] <= 100)
+		return 70;
+
+	for (ratio = ENH_NUM_BINS - 1; ratio >= 0 ; ratio--) {
+		distortion = 0;
+		for (i = ratio; i < ENH_NUM_BINS; i++) {
+			int pixel_distortion = (i - ratio)*8;
+			int num_pixels = levels[i];
+			distortion += num_pixels * pixel_distortion;
+		}
+		if (distortion > target)
+			break;
+		else
+			prev_distortion = distortion;
+	}
+
+	ratio++;
+
+	/* If we're not exactly at the border between two buckets, extrapolate
+	 * to get 3 extra bits of accuracy.
+	 */
+	if (distortion - prev_distortion)
+		off = 8 * (target - prev_distortion) /
+		      (distortion - prev_distortion);
+	else
+		off = 0;
+
+	final_ratio = ratio * 255 / 31 + off;
+
+	if (final_ratio > 255)
+		final_ratio = 255;
+
+	/* Never aim for less than 50% of the total backlight */
+	if (final_ratio < 128)
+		final_ratio = 128;
+
+	return final_ratio;
+}
+
+static void get_levels(struct drm_device *dev, int pipe, int *levels)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int i;
+
+	for (i = 0; i < ENH_NUM_BINS; i++) {
+		u32 hist_ctl = ENH_HIST_ENABLE |
+			       ENH_MODIF_TBL_ENABLE |
+			       ENH_PIPE(pipe) |
+			       HIST_MODE_YUV |
+			       ENH_MODE_ADDITIVE |
+			       i;
+
+		/* Ivb workaround, see the explanation at the top */
+		if (INTEL_INFO(dev)->gen == 7)
+			hist_ctl &= ~ENH_MODIF_TBL_ENABLE;
+
+		I915_WRITE(BLM_HIST_CTL, hist_ctl);
+
+		levels[i] = I915_READ(BLM_HIST_ENH);
+	}
+}
+
+/* Multiplier is 16.16 fixed point */
+static void set_levels(struct drm_device *dev, int pipe, int multiplier)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int i;
+
+	if (INTEL_INFO(dev)->gen == 7) {
+		/* Ivb workaround, see the explanation at the top */
+		for (i = 0; i < 256; i++) {
+			int v = intel_fixed_div(i, multiplier);
+			if (v > 255)
+				v = 255;
+			v = v | (v << 8) | (v << 16);
+			I915_WRITE(LGC_PALETTE(pipe) + i * 4, v);
+		}
+
+		return;
+	}
+
+	for (i = 0; i < ENH_NUM_BINS; i++) {
+		int base_value = i * 8 * 4;
+		int level = base_value -
+			    intel_fixed_mul(base_value, multiplier);
+		I915_WRITE(BLM_HIST_CTL, ENH_HIST_ENABLE |
+					 ENH_MODIF_TBL_ENABLE |
+					 ENH_PIPE(pipe) |
+					 HIST_MODE_YUV |
+					 ENH_MODE_ADDITIVE |
+					 BIN_REGISTER_SET |
+					 i);
+		I915_WRITE(BLM_HIST_ENH, level);
+	}
+}
+
+/* Compute the current step. Returns true if we need to change the levels,
+ * false otherwise.
+ */
+static bool adaptive_backlight_current_step(drm_i915_private_t *dev_priv,
+					   int correction_level)
+{
+	int delta, direction;
+
+	direction = (correction_level >
+			dev_priv->backlight_correction_level);
+
+	if (direction == dev_priv->backlight_correction_direction) {
+		dev_priv->backlight_correction_count++;
+	} else {
+		dev_priv->backlight_correction_count = 0;
+		dev_priv->backlight_correction_direction = direction;
+	}
+
+	delta = abs(correction_level -
+			dev_priv->backlight_correction_level)/4;
+
+	if (delta < 1)
+		delta = 1;
+
+	/* For increasing the brightness, we do it instantly.
+	 * For lowering the brightness, we require at least 10 frames
+	 * below the current value. This avoids ping-ponging of the
+	 * backlight level.
+	 *
+	 * We also never increase the backlight by more than 6% per
+	 * frame, and never lower it by more than 3% per frame, because
+	 * the backlight needs time to adjust and the LCD correction
+	 * would be "ahead" otherwise.
+	 */
+	if (correction_level > dev_priv->backlight_correction_level) {
+		if (delta > 15)
+			delta = 15;
+		dev_priv->backlight_correction_level += delta;
+	} else if ((dev_priv->backlight_correction_count > 10) &&
+			(correction_level < dev_priv->backlight_correction_level)) {
+		if (delta > 7)
+			delta = 7;
+		dev_priv->backlight_correction_level -= delta;
+	} else {
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * This function computes the backlight correction level for an acceptable
+ * distortion and fills up the correction bins adequately.
+ */
+static void
+adaptive_backlight_correct(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int correction_level;
+	int multiplier, one_over_gamma;
+	int levels[ENH_NUM_BINS];
+
+	get_levels(dev, pipe, levels);
+
+	/* Find the correction level for an acceptable distortion */
+	correction_level = histogram_find_correction_level(levels);
+
+	/* If we're already at our correction target, then there is
+	 * nothing to do
+	 */
+	if (dev_priv->backlight_correction_level == correction_level)
+		return;
+
+	/* Decide by how much to move this step. If we didn't move, return */
+	if (!adaptive_backlight_current_step(dev_priv, correction_level))
+		return;
+
+	dev_priv->set_backlight(dev, dev_priv->backlight_level);
+
+	/* We need to invert the gamma correction of the LCD values,
+	 * but not of the backlight which is linear.
+	 */
+	one_over_gamma = intel_fixed_div(FIXED_ONE,
+			dev_priv->adaptive_backlight_panel_gamma);
+	multiplier = intel_fixed_pow(dev_priv->backlight_correction_level * 256,
+			one_over_gamma);
+
+	set_levels(dev, pipe, multiplier);
+}
+
+void intel_adaptive_backlight(struct drm_device *dev, int pipe_vblank_event)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	int pipe;
+	struct drm_connector *connector;
+	struct intel_crtc *intel_crtc;
+	bool found = false;
+
+	if (!dev_priv->adaptive_backlight_enabled)
+		return;
+
+	/* Find the connector */
+	list_for_each_entry(connector,
+			    &dev->mode_config.connector_list,
+			    head)
+		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+			found = true;
+			break;
+		}
+
+	if (!found)
+		return;
+
+	if (!connector)
+		return;
+
+	if (!connector->encoder)
+		return;
+
+	if (!connector->encoder->crtc)
+		return;
+
+	/* Find the pipe for the panel. */
+	intel_crtc = to_intel_crtc(connector->encoder->crtc);
+	pipe = intel_crtc->pipe;
+
+	/* The callback happens for both pipe A & B. Now that we know which
+	 * pipe we're doing adaptive backlight on, check that it's the right
+	 * one. Bail if it isn't.
+	 */
+	if (pipe != pipe_vblank_event)
+		return;
+
+	/* Make sure we ack the previous event. Even though we do not get the
+	 * IRQs (see above explanation), we must still ack the events otherwise
+	 * the histogram data doesn't get updated any more.
+	 */
+	I915_WRITE(BLM_HIST_GUARD_BAND, BLM_HIST_INTR_ENABLE |
+					BLM_HIST_EVENT_STATUS |
+					(1 << BLM_HIST_INTR_DELAY_SHIFT));
+
+
+	adaptive_backlight_correct(dev, pipe);
+}
+
+void intel_adaptive_backlight_enable(struct drm_i915_private *dev_priv)
+{
+	dev_priv->backlight_correction_level = 256;
+	dev_priv->backlight_correction_count = 0;
+	dev_priv->backlight_correction_direction = 0;
+	/* Default gamma is 2.2 as 16.16 fixed point */
+	if (!dev_priv->adaptive_backlight_panel_gamma)
+		dev_priv->adaptive_backlight_panel_gamma = 144179;
+
+	dev_priv->adaptive_backlight_enabled = true;
+}
+
+void intel_adaptive_backlight_disable(struct drm_i915_private *dev_priv,
+				      struct drm_connector *connector)
+{
+	struct intel_crtc *intel_crtc;
+	int pipe;
+	struct drm_device *dev = dev_priv->dev;
+
+	dev_priv->adaptive_backlight_enabled = false;
+
+	dev_priv->backlight_correction_level = 256;
+
+	dev_priv->set_backlight(dev, dev_priv->backlight_level);
+
+	/* Find the pipe */
+	if (!connector->encoder)
+		return;
+
+	if (!connector->encoder->crtc)
+		return;
+
+	intel_crtc = to_intel_crtc(connector->encoder->crtc);
+	pipe = intel_crtc->pipe;
+
+	/* Reset the levels to default */
+	set_levels(dev, pipe, FIXED_ONE);
+}
+
+static u32 intel_link_get_backlight(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
+
+	val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
+
+	return (val - 2) / 4;
+}
+
+static u32 intel_link_get_max_backlight(struct drm_device *dev)
+{
+	return 255;
+}
+
+static void intel_link_set_backlight(struct drm_device *dev, u32 level)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 hw_level;
+	u32 val;
+
+	dev_priv->backlight_level = level;
+
+	if (dev_priv->adaptive_backlight_enabled)
+		level = level * dev_priv->backlight_correction_level >> 8;
+
+	if (level == 0)
+		hw_level = 0;
+	else
+		hw_level = level * 4 + 2;
+
+	val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
+	I915_WRITE(BLC_PWM_CPU_CTL, val | hw_level);
+}
+
+static void intel_link_disable_backlight(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->backlight_enabled = false;
+	dev_priv->set_backlight(dev, 0);
+}
+
+static void intel_link_enable_backlight(struct drm_device *dev, enum pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Increase the level from 0 */
+	if (dev_priv->backlight_level == 0)
+		dev_priv->backlight_level = dev_priv->get_max_backlight(dev);
+
+	dev_priv->backlight_enabled = true;
+	dev_priv->set_backlight(dev, dev_priv->backlight_level);
+}
+
+void intel_adaptive_backlight_setup(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	dev_priv->get_backlight = intel_link_get_backlight;
+	dev_priv->get_max_backlight = intel_link_get_max_backlight;
+	dev_priv->set_backlight = intel_link_set_backlight;
+	dev_priv->disable_backlight = intel_link_disable_backlight;
+	dev_priv->enable_backlight = intel_link_enable_backlight;
+
+	intel_adaptive_backlight_enable(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d5f3105..e5d16bc 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2442,6 +2442,23 @@ intel_dp_set_property(struct drm_connector *connector,
 		goto done;
 	}
 
+	if (property == dev_priv->adaptive_backlight_property) {
+		dev_priv->adaptive_backlight_enabled = !!val;
+
+		if (dev_priv->adaptive_backlight_enabled)
+			intel_adaptive_backlight_enable(dev_priv);
+		else
+			intel_adaptive_backlight_disable(dev_priv, connector);
+
+		goto done_nomodeset;
+	}
+
+	if (property == dev_priv->panel_gamma_property) {
+		dev_priv->adaptive_backlight_panel_gamma = (u32)val * 65536 / 100;
+
+		goto done_nomodeset;
+	}
+
 	return -EINVAL;
 
 done:
@@ -2451,6 +2468,7 @@ done:
 			       crtc->x, crtc->y, crtc->fb);
 	}
 
+done_nomodeset:
 	return 0;
 }
 
@@ -2575,6 +2593,12 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
 			DRM_MODE_SCALE_ASPECT);
 		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
 	}
+
+	if ((INTEL_INFO(connector->dev)->gen == 7) &&
+	    (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
+		intel_attach_adaptive_backlight_property(connector);
+		intel_attach_panel_gamma_property(connector);
+	}
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4f41b8a..0762970 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -423,6 +423,9 @@ int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 
 extern void intel_attach_force_audio_property(struct drm_connector *connector);
 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
+extern void
+intel_attach_adaptive_backlight_property(struct drm_connector *connector);
+extern void intel_attach_panel_gamma_property(struct drm_connector *connector);
 
 extern void intel_crt_init(struct drm_device *dev);
 extern void intel_hdmi_init(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_fixedpoint.h b/drivers/gpu/drm/i915/intel_fixedpoint.h
new file mode 100644
index 0000000..0e9343b
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_fixedpoint.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2012 The Chromium OS Authors.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * The backlight is corrected in linear space. However the LCD correction is
+ * corrected in gamma space. So to be able to compute the correction value for
+ * the LCD, we have to compute the inverse gamma. To do so, we carry this
+ * small fixed point module which allows us to use pow() to compute inverse
+ * gamma.
+ *
+ * The fixed point format used here is 16.16.
+ */
+
+/* intel_fixed_exp_tbl[x*32] = exp(x) * 65536 */
+static const int intel_fixed_exp_tbl[33] = {
+0x00010000, 0x00010820, 0x00011083, 0x00011929, 0x00012216, 0x00012b4b,
+0x000134cc, 0x00013e99, 0x000148b6, 0x00015325, 0x00015de9, 0x00016905,
+0x0001747a, 0x0001804d, 0x00018c80, 0x00019916, 0x0001a613, 0x0001b378,
+0x0001c14b, 0x0001cf8e, 0x0001de45, 0x0001ed74, 0x0001fd1e, 0x00020d47,
+0x00021df4, 0x00022f28, 0x000240e8, 0x00025338, 0x0002661d, 0x0002799b,
+0x00028db8, 0x0002a278, 0x0002b7e1
+};
+
+/* intel_fixed_log_tbl[x*32] = log(x) * 65536 */
+static const int intel_fixed_log_tbl[33] = {
+0x80000000, 0xfffc88c6, 0xfffd3a38, 0xfffda204, 0xfffdebaa, 0xfffe24ca,
+0xfffe5376, 0xfffe7aed, 0xfffe9d1c, 0xfffebb43, 0xfffed63c, 0xfffeeea2,
+0xffff04e8, 0xffff1966, 0xffff2c5f, 0xffff3e08, 0xffff4e8e, 0xffff5e13,
+0xffff6cb5, 0xffff7a8c, 0xffff87ae, 0xffff942b, 0xffffa014, 0xffffab75,
+0xffffb65a, 0xffffc0ce, 0xffffcad8, 0xffffd481, 0xffffddd1, 0xffffe6cd,
+0xffffef7a, 0xfffff7df, 0xffffffff
+};
+
+/* e * 65536 */
+#define FIXED_E (intel_fixed_exp_tbl[32])
+/* 1 * 65536 */
+#define FIXED_ONE 65536
+
+static int intel_fixed_mul(int a, int b)
+{
+	int64_t p = (int64_t)a * b;
+	do_div(p, 65536);
+	return (int)p;
+}
+
+static int intel_fixed_div(int a, int b)
+{
+	int64_t p = (int64_t)a * 65536;
+	do_div(p, b);
+	return (int)p;
+}
+
+/*
+ * Approximate fixed point log function.
+ * Only works for inputs in [0,1[
+ */
+static int intel_fixed_log(int val)
+{
+	int index = val * 32 / FIXED_ONE;
+	int remainder = (val & 0x7ff) << 5;
+	int v1 = intel_fixed_log_tbl[index];
+	int v2 = intel_fixed_log_tbl[index+1];
+	int final = v1 + intel_fixed_mul(v2 - v1, remainder);
+	return final;
+}
+
+/*
+ * Approximate fixed point exp function.
+ */
+static int intel_fixed_exp(int val)
+{
+	int count = 0;
+	int index, remainder;
+	int int_part = FIXED_ONE, frac_part;
+	int i, v, v1, v2;
+
+	while (val < 0) {
+		val += FIXED_ONE;
+		count--;
+	}
+
+	while (val > FIXED_ONE) {
+		val -= FIXED_ONE;
+		count++;
+	}
+
+	index = val * 32 / FIXED_ONE;
+	remainder = (val & 0x7ff) << 5;
+
+	v1 = intel_fixed_exp_tbl[index];
+	v2 = intel_fixed_exp_tbl[index+1];
+	frac_part = v1 + intel_fixed_mul(v2 - v1, remainder);
+
+	if (count < 0) {
+		for (i = 0; i < -count; i++)
+			int_part = intel_fixed_mul(int_part, FIXED_E);
+
+		v = intel_fixed_div(frac_part, int_part);
+	} else {
+		for (i = 0; i < count; i++)
+			int_part = intel_fixed_mul(int_part, FIXED_E);
+
+		v = intel_fixed_mul(frac_part, int_part);
+	}
+	return (v >= 0) ? v : 0;
+}
+
+/*
+ * Approximate fixed point pow function.
+ * Only works for x in [0,1[
+ */
+static int intel_fixed_pow(int x, int y)
+{
+	int e, p, r;
+	e = intel_fixed_log(x);
+	p = intel_fixed_mul(e, y);
+	r = intel_fixed_exp(p);
+	return r;
+}
+
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index 0d9b115..57b9d52 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -100,6 +100,54 @@ intel_attach_force_audio_property(struct drm_connector *connector)
 	drm_object_attach_property(&connector->base, prop, 0);
 }
 
+static const struct drm_prop_enum_list adaptive_backlight_names[] = {
+	{ 0, "off" },
+	{ 1, "on" },
+};
+
+void
+intel_attach_adaptive_backlight_property(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_property *prop;
+
+	prop = dev_priv->adaptive_backlight_property;
+	if (prop == NULL) {
+		prop = drm_property_create_enum(dev, 0,
+					"Adaptive backlight",
+					adaptive_backlight_names,
+					ARRAY_SIZE(adaptive_backlight_names));
+		if (prop == NULL)
+			return;
+
+		dev_priv->adaptive_backlight_property = prop;
+	}
+	drm_object_attach_property(&connector->base, prop, 0);
+}
+
+void
+intel_attach_panel_gamma_property(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_property *prop;
+
+	prop = dev_priv->panel_gamma_property;
+	if (prop == NULL) {
+		prop = drm_property_create_range(dev, 0,
+					"Panel gamma",
+					100,
+					550);
+
+		if (prop == NULL)
+			return;
+
+		dev_priv->panel_gamma_property = prop;
+	}
+	drm_object_attach_property(&connector->base, prop, 100);
+}
+
 static const struct drm_prop_enum_list broadcast_rgb_names[] = {
 	{ 0, "Full" },
 	{ 1, "Limited 16:235" },
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index dddd4a1..cebabb0 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -30,6 +30,7 @@
 
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
+#include <linux/dmi.h>
 #include <linux/moduleparam.h>
 #include "intel_drv.h"
 #include "i915_drv.h"
@@ -392,6 +393,23 @@ set_level:
 	intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
 }
 
+static int intel_link_backlight(const struct dmi_system_id *id)
+{
+	DRM_DEBUG_KMS("Using Link backlight\n");
+	return 1;
+}
+
+static const struct dmi_system_id link_dmi_table[] = {
+	{
+		.callback = intel_link_backlight,
+		.ident = "Link",
+		.matches = {
+			DMI_MATCH(DMI_PRODUCT_NAME, "Link"),
+		},
+	},
+	{ }
+};
+
 static void intel_panel_init_backlight(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -404,6 +422,26 @@ static void intel_panel_init_backlight(struct drm_device *dev)
 
 	dev_priv->backlight_level = dev_priv->get_backlight(dev);
 	dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
+
+	if (dmi_check_system(link_dmi_table)) {
+		struct drm_connector *connector;
+		bool found = false;
+		/* Find the connector */
+		list_for_each_entry(connector,
+				    &dev->mode_config.connector_list,
+				    head)
+			if (connector->connector_type ==
+			    DRM_MODE_CONNECTOR_eDP) {
+				found = true;
+				break;
+			}
+
+		if (found) {
+			intel_adaptive_backlight_setup(dev);
+			intel_attach_adaptive_backlight_property(connector);
+			intel_attach_panel_gamma_property(connector);
+		}
+	}
 }
 
 enum drm_connector_status
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: set enable_rc6 to per-chip default.

[james.ausmus]

From: Todd Broch <tbroch@chromium.org>

BUG=chrome-os-partner:10516
TEST=manual,
1. Run on several platforms.  Measure RAPL power @idle.
2. Check for general platform stability

Change-Id: Ia3c8f1f48eb39ae0fb6e0f6e86b4beb1d2155554
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/29677
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4c4cfdb..fe6d228 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -63,7 +63,7 @@ module_param_named(semaphores, i915_semaphores, int, 0600);
 MODULE_PARM_DESC(semaphores,
 		"Use semaphores for inter-ring sync (default: true)");
 
-int i915_enable_rc6 __read_mostly = 1;
+int i915_enable_rc6 __read_mostly = -1;
 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 MODULE_PARM_DESC(i915_enable_rc6,
 		"Enable power-saving render C-state 6. "
-- 
1.8.3.2

[PATCH] CHROMIUM: gpu: i915: optimize vblank timeout

[james.ausmus]

From: Vincent Palatin <vpalatin@chromium.org>

On the resume path, wait_for_vblank is called 4 times and waits until its
timeout. To reduce the delays on that path, let's compute the maximum vblank
delay instead of always using the arbitrary 50 ms value.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=chrome-os-partner:13364
TEST=On Link, measure resume time and see a 130ms improvement.

Change-Id: I88231de43573432b6d71255f622eb9860fe3c28d
Reviewed-on: https://gerrit.chromium.org/gerrit/34624
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
[marcheu: fixup for 3.8 rebase]
---
 drivers/gpu/drm/i915/intel_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index da1ad9c..0bc822e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -967,6 +967,9 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipestat_reg = PIPESTAT(pipe);
+	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+	int timeout = crtc->hwmode.vrefresh ?
+		DIV_ROUND_UP(1000, crtc->hwmode.vrefresh) : 50;
 
 	if (INTEL_INFO(dev)->gen >= 5) {
 		ironlake_wait_for_vblank(dev, pipe);
@@ -992,7 +995,7 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 	/* Wait for vblank interrupt bit to set */
 	if (wait_for(I915_READ(pipestat_reg) &
 		     PIPE_VBLANK_INTERRUPT_STATUS,
-		     50))
+		     timeout))
 		DRM_DEBUG_KMS("vblank wait timed out\n");
 }
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: i915: Allow 0 level when turning on backlight.

[james.ausmus]

From: Daniel Erat <derat@chromium.org>

Previously, the i915 panel driver would set the backlight to
its maximum level if the level was 0 when turning the
display on.  We don't need this (powerd already does it),
and removing it avoids a potential race where we jump to
100% brightness when the brightness-up key is pressed due to
Chrome turning on the display before powerd sets a non-zero
level.

BUG=chromium-os:31795,chromium-os:32447,chromium-os:35481
TEST=manual: no bright flash when increasing the backlight
     from 0% on lumpy or resuming from suspend
CQ-DEPEND=I26f11562df8e01927c0220cddd91e665fe087be9
CQ-DEPEND=Ia961baae656044c3713fb967d8ad173d317c4217

Signed-off-by: Daniel Erat <derat@chromium.org>
Change-Id: I4bafa1c2e1254b09906245b59c935a4be1088d71
Reviewed-on: https://gerrit.chromium.org/gerrit/36135
Reviewed-by: Simon Que <sque@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
[marcheu: fixup for 3.8 rebase]
---
 drivers/gpu/drm/i915/i915_drv.h    | 1 +
 drivers/gpu/drm/i915/intel_panel.c | 9 ++++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 646c3eb..806a694 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -700,6 +700,7 @@ typedef struct drm_i915_private {
 
 	/* LVDS info */
 	int backlight_level;  /* restore backlight to this value */
+	bool backlight_level_has_been_set;
 	bool backlight_enabled;
 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 92678f6..abc7064 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -319,6 +319,8 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	dev_priv->backlight_level = level;
+	if (level > 0)
+		dev_priv->backlight_level_has_been_set = true;
 	if (dev_priv->backlight_enabled)
 		intel_panel_actually_set_backlight(dev, level);
 }
@@ -350,7 +352,11 @@ static void intel_panel_enable_backlight(struct drm_device *dev,
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (dev_priv->backlight_level == 0)
+	/* Increase the level from 0 unless someone in userspace has requested a
+	 * nonzero level at least once already -- in that case, we assume that
+	 * they know what they're doing and will raise the level themselves. */
+	if (dev_priv->backlight_level == 0 &&
+	    !dev_priv->backlight_level_has_been_set)
 		dev_priv->backlight_level = dev_priv->get_max_backlight(dev);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
@@ -424,6 +430,7 @@ static void intel_panel_init_backlight(struct drm_device *dev)
 	dev_priv->enable_backlight = intel_panel_enable_backlight;
 
 	dev_priv->backlight_level = dev_priv->get_backlight(dev);
+	dev_priv->backlight_level_has_been_set = false;
 	dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
 
 	if (dmi_check_system(link_dmi_table)) {
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Check the current edp backlight state before changing it.

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

This speeds up boot and suspend/resume times.

BUG=chrome-os-partner:13364
TEST=by hand

Change-Id: I8d7b7a22c50bcf32828d492e123ce301cefa297d
Reviewed-on: https://gerrit.chromium.org/gerrit/37047
Reviewed-by: Simon Que <sque@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 29013de..f763d45 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1195,6 +1195,10 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 		return;
 
 	DRM_DEBUG_KMS("\n");
+	pp = ironlake_get_pp_control(dev_priv);
+	if (pp & EDP_BLC_ENABLE)
+		return;
+
 	/*
 	 * If we enable the backlight right away following a panel power
 	 * on, we may see slight flicker as the panel syncs with the eDP
@@ -1202,7 +1206,6 @@ void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
 	 * allowing it to appear.
 	 */
 	msleep(intel_dp->backlight_on_delay);
-	pp = ironlake_get_pp_control(dev_priv);
 	pp |= EDP_BLC_ENABLE;
 	I915_WRITE(PCH_PP_CONTROL, pp);
 	POSTING_READ(PCH_PP_CONTROL);
@@ -1223,6 +1226,8 @@ void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
 
 	DRM_DEBUG_KMS("\n");
 	pp = ironlake_get_pp_control(dev_priv);
+	if (!(pp & EDP_BLC_ENABLE))
+		return;
 	pp &= ~EDP_BLC_ENABLE;
 	I915_WRITE(PCH_PP_CONTROL, pp);
 	POSTING_READ(PCH_PP_CONTROL);
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Workaround disappearing AVI Infoframe on resume

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

The AVI Infoframe disappears on SNB after suspend/resume. This patch
works around what seems to be a hardware issue by doing a dummy register
write on DPMS calls.

BUG=chrome-os-partner:16054
TEST=with the HDMI analyzer: suspend/resume parrot, verify that
TEST=the AVI infoframe is still here

Change-Id: I7cb880408db3cd279d09cb7a53f6787c14e03027
Reviewed-on: https://gerrit.chromium.org/gerrit/37596
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Stuart Abercrombie <sabercrombie@chromium.org>
Commit-Ready: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 2ee9821..3085e2b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -746,6 +746,12 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 		I915_WRITE(intel_hdmi->sdvox_reg, temp);
 		POSTING_READ(intel_hdmi->sdvox_reg);
 	}
+
+	/* Workaround for disappearing AVI Infoframe on SNB on resume */
+	if (HAS_PCH_SPLIT(dev)) {
+		I915_WRITE(_VIDEO_DIP_CTL_A, I915_READ(_VIDEO_DIP_CTL_A));
+		I915_WRITE(_VIDEO_DIP_CTL_B, I915_READ(_VIDEO_DIP_CTL_B));
+	}
 }
 
 static int intel_hdmi_mode_valid(struct drm_connector *connector,
-- 
1.8.3.2

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[PATCH] CHROMIUM: Partial revert of 24929352481f085c5f85d4d4cbc919ddf106d381

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

This is a partial revert of:
drm/i915: read out the modeset hw state at load and resume time
which fixes modeset on boot on alex on 3.8.

BUG=chromium-os:38961
TEST=boot alex with 3.8, see a picture

Change-Id: Id6efac800f4007ded759d237af5643d94ad839c3
---
 drivers/gpu/drm/i915/intel_display.c | 105 ++++++++++++++++++-----------------
 1 file changed, 55 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0bc822e..cc2db39 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7514,6 +7514,60 @@ free_work:
 	return ret;
 }
 
+static void intel_sanitize_modesetting(struct drm_device *dev,
+				       int pipe, int plane)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 reg, val;
+	int i;
+
+	/* Clear any frame start delays used for debugging left by the BIOS */
+	for_each_pipe(i) {
+		reg = PIPECONF(i);
+		I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
+	}
+
+	if (HAS_PCH_SPLIT(dev))
+		return;
+
+	/* Who knows what state these registers were left in by the BIOS or
+	 * grub?
+	 *
+	 * If we leave the registers in a conflicting state (e.g. with the
+	 * display plane reading from the other pipe than the one we intend
+	 * to use) then when we attempt to teardown the active mode, we will
+	 * not disable the pipes and planes in the correct order -- leaving
+	 * a plane reading from a disabled pipe and possibly leading to
+	 * undefined behaviour.
+	 */
+
+	reg = DSPCNTR(plane);
+	val = I915_READ(reg);
+
+	if ((val & DISPLAY_PLANE_ENABLE) == 0)
+		return;
+	if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
+		return;
+
+	/* This display plane is active and attached to the other CPU pipe. */
+	pipe = !pipe;
+
+	/* Disable the plane and wait for it to stop reading from the pipe. */
+	intel_disable_plane(dev_priv, plane, pipe);
+	intel_disable_pipe(dev_priv, pipe);
+}
+
+static void intel_crtc_reset(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+	/* We need to fix up any BIOS configuration that conflicts with
+	 * our expectations.
+	 */
+	intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
+}
+
 static struct drm_crtc_helper_funcs intel_helper_funcs = {
 	.mode_set_base_atomic = intel_pipe_set_base_atomic,
 	.load_lut = intel_crtc_load_lut,
@@ -8296,6 +8350,7 @@ out_config:
 }
 
 static const struct drm_crtc_funcs intel_crtc_funcs = {
+	.reset = intel_crtc_reset,
 	.cursor_set = intel_crtc_cursor_set,
 	.cursor_move = intel_crtc_cursor_move,
 	.gamma_set = intel_crtc_gamma_set,
@@ -9040,25 +9095,6 @@ static void intel_enable_pipe_a(struct drm_device *dev)
 
 }
 
-static bool
-intel_check_plane_mapping(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
-	u32 reg, val;
-
-	if (dev_priv->num_pipe == 1)
-		return true;
-
-	reg = DSPCNTR(!crtc->plane);
-	val = I915_READ(reg);
-
-	if ((val & DISPLAY_PLANE_ENABLE) &&
-	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
-		return false;
-
-	return true;
-}
-
 static void intel_sanitize_crtc(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
@@ -9069,37 +9105,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
 	reg = PIPECONF(crtc->cpu_transcoder);
 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 
-	/* We need to sanitize the plane -> pipe mapping first because this will
-	 * disable the crtc (and hence change the state) if it is wrong. Note
-	 * that gen4+ has a fixed plane -> pipe mapping.  */
-	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
-		struct intel_connector *connector;
-		bool plane;
-
-		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
-			      crtc->base.base.id);
-
-		/* Pipe has the wrong plane attached and the plane is active.
-		 * Temporarily change the plane mapping and disable everything
-		 * ...  */
-		plane = crtc->plane;
-		crtc->plane = !plane;
-		dev_priv->display.crtc_disable(&crtc->base);
-		crtc->plane = plane;
-
-		/* ... and break all links. */
-		list_for_each_entry(connector, &dev->mode_config.connector_list,
-				    base.head) {
-			if (connector->encoder->base.crtc != &crtc->base)
-				continue;
-
-			intel_connector_break_all_links(connector);
-		}
-
-		WARN_ON(crtc->active);
-		crtc->base.enabled = false;
-	}
-
 	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
 	    crtc->pipe == PIPE_A && !crtc->active) {
 		/* BIOS forgot to enable pipe A, this mostly happens after
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: bounds check execbuffer relocations

[james.ausmus]

From: Kees Cook <keescook@chromium.org>

It is possible to wrap the counter used to allocate the buffer for
relocation copies. This could lead to heap writing overflows.

BUG=chromium-os:39733
TEST=link build, PoC fails

[sending upstream]

Change-Id: Ifdd4ae846042852a4462d70cfa3c3b84d5a9d133
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/45118
Reviewed-by: Jorge Lucangeli Obes <jorgelo@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 26d08bb..b23d6cd 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -706,6 +706,7 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 		   int count)
 {
 	int i;
+	int total = 0;
 
 	for (i = 0; i < count; i++) {
 		char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
@@ -715,6 +716,9 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
 		if (exec[i].relocation_count >
 		    INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
 			return -EINVAL;
+		if (exec[i].relocation_count > INT_MAX - total)
+			return -EINVAL;
+		total += exec[i].relocation_count;
 
 		length = exec[i].relocation_count *
 			sizeof(struct drm_i915_gem_relocation_entry);
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Improve RC6p stability

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

When the CPU is loaded and the GPU tries to switch RC6p modes, the GPU
sometimes gets stuck in RC6p mode and doesn't come out of it. I suspect
that our voltage rail is too weak and sometimes falls behind.

This change throttles down the number of RC6p transitions we do to appease it.

The change also disables clock gating which seems to help. Upstream commit
which does that is 0f846f81a154cc1818416918d22939bda73da194
(drm/i915: disable RCBP and VDS unit clock gating on SNB and VL)

I tested this on multiple Link machines for hours. The number of RC6 problems
went down from ~ one every 15 minutes to ~ one every 25 hours. So this is not
a complete solution, but I suspect there might be another, more difficult to
reproduce, problem. In any case it reduces the issue significantly, to the
point where we might be able to forget about it.

I measured the power usage on idle before/after this patch and saw no
difference. Obviously when the GPU load varies, it will consume more power
since it now takes more time to adapt.

Also note that not all machines seem to react equally. Some crash fairly
often, and some less often. So this will improve the situation to different
extents for different people.

BUG=chrome-os-partner:16886,chrome-os-partner:11474
TEST=ran the factory stress test (RunIn.Stress) on multiple Link machines for
TEST=about 100 hours, saw only 4 RC6 crashes.

Change-Id: I1135d90e2a155424388d23c6e0879a210b4a0146
[sonnyrao: 3.8: parts upstream, move RC6p_THRESHOLD change to intel_pm.c]
Reviewed-on: https://gerrit.chromium.org/gerrit/42084
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e1c629..c86f432 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2573,7 +2573,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
-	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
+	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
 	/* Check if we are enabling RC6 */
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915/intel_i2c: enable 400kHz GMBUS for atmel_mxt devices

[james.ausmus]

From: Daniel Kurtz <djkurtz@chromium.org>

i915 gmbus writes at 400kHz should now work properly.

So, enable 400kHz and the native gmbus algorithm by default, but limit
to known high speed devices:
  * atmel_mxt devices on vga ddc
  * atmel_mxt devices (app mode and bootloader) on panel ddc

After further testing, this can be enabled for all devices and ddc
adapters.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>

BUG=chromium-os:26118,chrome-os-partner:8547,chrome-os-partner:8732
TEST=compiles clean; i915 driver successfully communicates to i2c devices
  on the vga and panel ddc adapters.
  Tested using an atmel i2c touchpad and atmel_mxt_ts driver.
TEST=place valid atmel mxt firmware at /lib/firmware/maxtouch.fw
  time echo 1 > update_fw
  Check that firmware update succeeds, and that the time is less than 18s.
  time echo 1 > update_fw

  real	0m17.923s
  user	0m0.000s
  sys	0m0.188s

This is a squash of three commits onto v3.4-rc5+danvet/intel-drm-next:

Change-Id: Id911a732409b06a4b0a654270d548929e2887582
Reviewed-on: https://gerrit.chromium.org/gerrit/17938

Change-Id: Ide237fbe6c33b17395d8398af1b691db69eb3036
Reviewed-on: https://gerrit.chromium.org/gerrit/18425

Change-Id: Ic5741b98b30c522acd3bee0a92041e08993e950e
Reviewed-on: https://gerrit.chromium.org/gerrit/21833
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_i2c.c | 10 +++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 59afb7e..27ef35a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -865,6 +865,7 @@
 #define   GMBUS_RATE_50KHZ	(1<<8)
 #define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
 #define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
+#define   GMBUS_RATE_MASK	(3<<8)
 #define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
 #define   GMBUS_PORT_DISABLED	0
 #define   GMBUS_PORT_SSC	1
@@ -875,6 +876,7 @@
 #define   GMBUS_PORT_DPD	6 /* HDMID */
 #define   GMBUS_PORT_RESERVED	7 /* 7 reserved */
 #define   GMBUS_NUM_PORTS	(GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
+#define   GMBUS_PORT_MASK	7
 #define GMBUS1			0x5104 /* command/status */
 #define   GMBUS_SW_CLR_INT	(1<<31)
 #define   GMBUS_SW_RDY		(1<<30)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 3ef5af1..364204f 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -332,6 +332,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
 	struct drm_i915_private *dev_priv = bus->dev_priv;
 	int i, reg_offset;
 	int ret = 0;
+	u32 gmbus0;
 
 	mutex_lock(&dev_priv->gmbus_mutex);
 
@@ -342,7 +343,14 @@ gmbus_xfer(struct i2c_adapter *adapter,
 
 	reg_offset = dev_priv->gpio_mmio_base;
 
-	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
+	/* Hack to use 400kHz only for atmel_mxt i2c devices on ddc ports */
+	gmbus0 = bus->reg0;
+	if (((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_VGADDC &&
+	     msgs[0].addr == 0x4b) ||
+	    ((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_PANEL &&
+	     (msgs[0].addr == 0x4a || msgs[0].addr == 0x26)))
+		gmbus0 = (gmbus0 & ~GMBUS_RATE_MASK) | GMBUS_RATE_400KHZ;
+	I915_WRITE(GMBUS0 + reg_offset, gmbus0);
 
 	for (i = 0; i < num; i++) {
 		u32 gmbus2;
-- 
1.8.3.2

[PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for cyapa

[james.ausmus]

From: Benson Leung <bleung@chromium.org>

Allow 400khz mode on port2, VGADDC address 0x67 for
cyapa i2c touchpads. This will improve firmware
update speed.

BUG=chrome-os-partner:9798
TEST=time echo 1 > /sys/bus/i2c/devices/2-0067/update_fw
Check that the update firmware succeeds, and the time
taken was:
real	0m13.823s
user	0m0.000s
sys	0m0.121s

Change-Id: I38afaef60f1421003a1e54f4108f465ba4ce7899
Signed-off-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/22990
Reviewed-by: Yufeng Shen <miletus@chromium.org>
---
 drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 364204f..6d9364c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -343,10 +343,10 @@ gmbus_xfer(struct i2c_adapter *adapter,
 
 	reg_offset = dev_priv->gpio_mmio_base;
 
-	/* Hack to use 400kHz only for atmel_mxt i2c devices on ddc ports */
+	/* Hack to use 400kHz only for touch i2c devices on ddc ports */
 	gmbus0 = bus->reg0;
 	if (((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_VGADDC &&
-	     msgs[0].addr == 0x4b) ||
+	     (msgs[0].addr == 0x4b || msgs[0].addr == 0x67)) ||
 	    ((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_PANEL &&
 	     (msgs[0].addr == 0x4a || msgs[0].addr == 0x26)))
 		gmbus0 = (gmbus0 & ~GMBUS_RATE_MASK) | GMBUS_RATE_400KHZ;
-- 
1.8.3.2

[PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for atmel mxt bl on VGADDC

[james.ausmus]

From: Benson Leung <bleung@chromium.org>

The atmel_mxt_ts bootloader mode can support 400khz operation
successfully. Enable it for bootloader at address 0x25 on the
VGADDC adapter.

BUG=chrome-os-partner:9994
TEST=place valid atmel mxt firmware at /lib/firmware/maxtouch.fw
time echo 1 > update_fw
Check that firmware update succeeds, and that the time is less than 9s.
time echo 1 > update_fw

real	0m8.450s
user	0m0.001s
sys	0m0.100s

Change-Id: I52373189e051c265ce32a99cee8b139f51721b28
Signed-off-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/23760
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
---
 drivers/gpu/drm/i915/intel_i2c.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 6d9364c..a18837f 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -346,10 +346,12 @@ gmbus_xfer(struct i2c_adapter *adapter,
 	/* Hack to use 400kHz only for touch i2c devices on ddc ports */
 	gmbus0 = bus->reg0;
 	if (((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_VGADDC &&
-	     (msgs[0].addr == 0x4b || msgs[0].addr == 0x67)) ||
+	     (msgs[0].addr == 0x4b || msgs[0].addr == 0x67 ||
+	      msgs[0].addr == 0x25)) ||
 	    ((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_PANEL &&
-	     (msgs[0].addr == 0x4a || msgs[0].addr == 0x26)))
+	     (msgs[0].addr == 0x4a || msgs[0].addr == 0x26))) {
 		gmbus0 = (gmbus0 & ~GMBUS_RATE_MASK) | GMBUS_RATE_400KHZ;
+	}
 	I915_WRITE(GMBUS0 + reg_offset, gmbus0);
 
 	for (i = 0; i < num; i++) {
-- 
1.8.3.2

[PATCH] CHROMIUM: drm/i915: fix resume

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

i915 resume relies on vt switch in kernel 3.8.

This is wrong on systems which don't vt switch, like Chrome OS.
Instead, we just save and restore the state properly across
suspend/resume by:
- not disabling everthying on suspend
- forcing a modeset on resume
- forcing a restore of the cursor state

BUG=chromium:221562
TEST=display is on after resume and I see a cursor

Change-Id: I4b59e91ac4770b847aa0821d1fd5394d7176af3c
Reviewed-on: https://gerrit.chromium.org/gerrit/50922
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.c      | 5 ++---
 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7610fbc..f31b530 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -483,8 +483,6 @@ static int i915_drm_freeze(struct drm_device *dev)
 
 		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 
-		intel_modeset_disable(dev);
-
 		drm_irq_uninstall(dev);
 	}
 
@@ -563,7 +561,8 @@ static int __i915_drm_thaw(struct drm_device *dev)
 		mutex_unlock(&dev->struct_mutex);
 
 		intel_modeset_init_hw(dev);
-		intel_modeset_setup_hw_state(dev, false);
+		intel_modeset_setup_hw_state(dev, true);
+
 		drm_irq_install(dev);
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d0b3b3..5dca437 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9367,6 +9367,10 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 			intel_set_mode(&crtc->base, &crtc->base.mode,
 				       crtc->base.x, crtc->base.y, crtc->base.fb);
+
+			/* Force-cycle the cursor */
+			crtc->cursor_visible = false;
+			intel_crtc_update_cursor(crtc, true);
 		}
 
 		i915_redisable_vga(dev);
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Fix warning

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

intel_crtc_update_cursor takes a drm_crtc but we were passing an
intel_crtc. Fix the warning by passing the base class.

BUG=none
TEST=compiles and runs on link

Change-Id: I487ef1984f7957b47bcc6e3edada8911224d8771
Reviewed-on: https://gerrit.chromium.org/gerrit/51383
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5dca437..64e4206 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9370,7 +9370,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
 
 			/* Force-cycle the cursor */
 			crtc->cursor_visible = false;
-			intel_crtc_update_cursor(crtc, true);
+			intel_crtc_update_cursor(&crtc->base, true);
 		}
 
 		i915_redisable_vga(dev);
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Initialize the backlight when reported max is 0

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

The i915 driver stopped doing this in 3.8. Chrome OS machines rely
on this initialization since they don't have a VBIOS.

BUG=chromium:242552
TEST=by hand on a stumpy which doesn't run the vbios: the backlight is non-zero

Change-Id: Ia76238a1e93e89a4f1434e88edb431225062f0e1
Reviewed-on: https://gerrit.chromium.org/gerrit/56134
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_panel.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index abc7064..a3d87a9 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -508,11 +508,7 @@ int intel_panel_setup_backlight(struct drm_connector *connector)
 
 	memset(&props, 0, sizeof(props));
 	props.type = BACKLIGHT_RAW;
-	props.max_brightness = _intel_panel_get_max_backlight(dev);
-	if (props.max_brightness == 0) {
-		DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
-		return -ENODEV;
-	}
+	props.max_brightness = intel_panel_get_max_backlight(dev);
 	dev_priv->backlight =
 		backlight_device_register("intel_backlight",
 					  &connector->kdev, dev,
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Don't evict bound object in the shrinker

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

Before swapping, the shrinker gets called on all drivers to try
and reclaim some memory before resorting to disk access. For
i915, the shrinker will eventually try to move objects out of
the GTT to make them swappable. However when this happens too
often, this will have two negative effects:

- once we have exhausted all the purgeable objects, the
  remaining objects will start bouncing in and out of the GTT
  as the rendering drags them in and the shrinker pulls them out

- the i915 shrinker needs to wait on the CPU for the GPU to
  complete pending rendering, which kills all asynchronicity

Those two things will slow down the system significantly as soon
as we start hitting the shrinker. So in this patch, we change
the shrinker to stop evicting in-use GTT objects. This avoids
both issues.

BUG=none
TEST=compiles and runs, seems to behave better under memory pressure

Change-Id: Iadb3c28575aae015f0f4b7c16f02e1e7ec6ef95a
Reviewed-on: https://gerrit.chromium.org/gerrit/57367
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/i915_gem.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index de45b60..3a72002 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4402,8 +4402,14 @@ i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
 		if (nr_to_scan > 0)
 			nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
 							false);
-		if (nr_to_scan > 0)
-			i915_gem_shrink_all(dev_priv);
+
+		/* We don't want to shrink all objects. When the shrinker is
+		 * called too often, this causes bouncing of GEM objects in
+		 * and out of the GTT, as well as GPU synchronization which
+		 * slows the system to a crawl.
+		 */
+		/*if (nr_to_scan > 0)
+			i915_gem_shrink_all(dev_priv);*/
 	}
 
 	cnt = 0;
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915/intel_drv: reduce wait_for polling time

[james.ausmus]

From: Daniel Kurtz <djkurtz@chromium.org>

Currently, 400kHz i2c transactions on i915 ddc adapters are gated by
long polling loops in the wait_for() macro.
For the case where the polling loops sleep, make them tighter by
converting a msleep(1) to usleep_range(50, 100);

A better solution might be to eliminate this polling entirely, and use
the i915 interrupts to detect state transitions instead of polling.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>

BUG=chromium:246465
TEST=i2c reads over ddc succeed.  On a scope, single transactions no
  longer have large gaps.

Change-Id: I96cef50ed8a3d0ad8a3c6fa6f079234242fa17d3
Reviewed-on: https://gerrit.chromium.org/gerrit/17937
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57458
Tested-by: Yufeng Shen <miletus@chromium.org>
Commit-Queue: Yufeng Shen <miletus@chromium.org>
---
 drivers/gpu/drm/i915/intel_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 60ec305..9f32cfc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -42,7 +42,7 @@
 			break;						\
 		}							\
 		if (W && drm_can_sleep())  {				\
-			msleep(W);					\
+			usleep_range(W * 50, W * 100);			\
 		} else {						\
 			cpu_relax();					\
 		}							\
-- 
1.8.3.2

[PATCH] CHROMIUM: drm/i915: tune the RC6 timeout for stability

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

It's basically the same deal as the RC6+ issues on ivy bridge
(https://gerrit.chromium.org/gerrit/#/c/42655/) except this
time with RC6 on sandy bridge. Like last time the core of the
issue is that the existing timings don't work 100% with our
voltage regulator, so once in a couple suspend/resumes the
kernel will print a warning message about the GPU not getting
out of RC6.

Luckily this time the shared timings are already working (from
the ivy bridge work) so we only need to adjust the one
RC6-specific timing, GEN6_RC6_THRESHOLD.

Just like with the RC6+ change, I couldn't see any measurable
power difference with an idle lumpy.

BUG=chromium:235116
TEST=ran the power_Resume a bunch on stumpy, didn't see an RC6 error
TEST=tested lumpy for power regressions on idle

Change-Id: I0e1be040e0e156cd38d6c396e237d4a01a16a6a2
Reviewed-on: https://gerrit.chromium.org/gerrit/57868
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1b487cb..8105d10 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2572,7 +2572,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
+	I915_WRITE(GEN6_RC6_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: repin bound framebuffers on resume

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

During suspend/resume all fences are reset, including their pin
count which is reset to 0. However a framebuffer can be bound across
suspend/resume, which means that after the buffer is unbound on
resume, the pin count for the buffer will be negative. Since the
fence pin count is now negative when available and zero when in use,
the buffer's fence will get recycled when the fence is in use which
is the opposite of what we want. The adverse effect is that since the
fence is recycled the tiling mode goes away while the buffer is being
displayed and we get lines/screens of garbage.

To fix this, we reallocate and repin the fences for all bound fbs on
resume, which ensures the pin count is right.

v2: Only repin the fence pin count, not the gem buffer pin count

BUG=chromium:219172,chromium:225056
TEST=by hand, suspend/resume on alex, the artifacts are gone

Change-Id: I5f623a583fe475561cc6643bdf52e7744740b4f1
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47933
Reviewed-on: https://gerrit.chromium.org/gerrit/57379
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/i915/i915_drv.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cc97082..873a66c1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -452,6 +452,32 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
 	return 1;
 }
 
+/* Repin all fbs which are currently bound to a crtc on resume */
+static void i915_repin_bound_fbs(struct drm_device *dev)
+{
+	struct drm_crtc *crtc;
+	struct drm_i915_gem_object *obj;
+	int ret;
+
+	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+		if (!crtc || !crtc->fb)
+			continue;
+		obj = to_intel_framebuffer(crtc->fb)->obj;
+		if (!obj)
+			continue;
+
+		/* Install a fence for tiled scan-out. */
+		if (obj->tiling_mode != I915_TILING_NONE) {
+			ret = i915_gem_object_get_fence(obj);
+			if (ret)
+				DRM_ERROR("Couldn't get a fence\n");
+			else
+				i915_gem_object_pin_fence(obj);
+		}
+
+	}
+}
+
 static int i915_drm_freeze(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -550,6 +576,7 @@ static int __i915_drm_thaw(struct drm_device *dev)
 		error = i915_gem_init_hw(dev);
 		mutex_unlock(&dev->struct_mutex);
 
+		i915_repin_bound_fbs(dev);
 		intel_modeset_init_hw(dev);
 		intel_modeset_setup_hw_state(dev, true);
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: i915: fix max backlight in normal mode

[james.ausmus]

From: Sonny Rao <sonnyrao@chromium.org>

Fix the setting of max backlight value in the case where there's no VBIOS.
The earlier port of CHROMIUM: drivers: i915: Default backlight PWM frequency
missed this case.

BUG=chromium:244616
TEST=test lumpy at max brightness and make sure the backlight stays on

Change-Id: I24550c01605618c722a985c84e80a69756408f09
Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58337
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_panel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index f5e4be1..bacdf69 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -224,7 +224,7 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
 		 * default backlight PWM settings.
 		 */
 		i915_set_default_max_backlight(dev);
-		max = i915_read_blc_pwm_ctl(dev);
+		max = _intel_panel_get_max_backlight(dev);
 	}
 
 	DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Tune the rc6 value again

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

Apparently 150k doesn't work on snb. After probing the snb I have
here, 125k is the max that the hardware seems to work with, and
luckily it seems stable after 50 power_Resume runs. So let's use
that.

BUG=chromium:251989
TEST=see rc6 residency go up in /sys/kernel/debug/dri/0/i915_drpc_info

Change-Id: Id78546f939c3d321760e2c32a894cb5ef4118998
Reviewed-on: https://gerrit.chromium.org/gerrit/59359
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8105d10..a735190 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2572,7 +2572,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 150000);
+	I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

Right after resume, panther point chipsets seem to ignore all
register writes. But if you wait a bit and retry, everything works
fine. I empirically measured that the window where it is flakey lasts
around 25ms, so let's sleep 30ms after turning on the PCH clock.

BUG=chrome-os-partner:20542
TEST=by hand: resume parrot a couple times, everything works as expected

Change-Id: I3281ff8ef5f43f6f73088a47500a557839acbdc0
Reviewed-on: https://gerrit.chromium.org/gerrit/60164
Reviewed-by: Stuart Abercrombie <sabercrombie@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7d13b34..c933bfa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4833,6 +4833,15 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
 		POSTING_READ(PCH_DREF_CONTROL);
 		udelay(200);
 	}
+
+	/*
+	 * On resume, the PPT PCH doesn't seem to work right away, and
+	 * sometimes ignores register read/writes until it's completely up.
+	 * Waiting 30ms seems to be long enough to avoid this.
+	 */
+	if (dev_priv->pch_id == INTEL_PCH_PPT_DEVICE_ID_TYPE)
+		msleep(30);
+
 }
 
 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: set lower RC6_THRESHOLD for HSW

[james.ausmus]

From: Sameer Nanda <snanda@chromium.org>

On Sandybridge/Ivybridge platforms, a higher RC6_THRESHOLD is required
for stability reasons. On Haswell, however, this higher setting is
resulting in an additional ~800mW of power consumption in light GPU
usage scenarios such as blinking cursor. Lowering RC6_THRESHOLD to 50000
on Haswell does not seem to cause stability issues.

Therefore, on SNB/IVB keep the higher threshold for stability reasons,
but on HSW use the default 50000 threshold for power saving reasons.

BUG=chrome-os-partner:20744
TEST=1. On SNB (lumpy) and IVB (link) systems, "intel_reg_read 0xa0b8"
command should return 0x1E848.
2. On Haswell systems, "intel_reg_read 0xa0b8" command should return
0xC350.

Change-Id: I2f7d5895b925dcf3ff96a2756e699797bda4104d
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61302
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a701495..56e65f9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3166,7 +3166,10 @@ static void gen6_enable_rps(struct drm_device *dev)
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
-	I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
+	if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
+		I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
+	else
+		I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
 	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: set linetime WM based on target_clock

[james.ausmus]

From: Sameer Nanda <snanda@chromium.org>

This is a regression from the initial i915 PC7 sandbox branch to the one
that finally got merged. It is resulting in increased power draw of
~1W due to low PC7 residency. Pulling this in as a CHROMIUM fix for now
till it gets resolved upstream.

BUG=chrome-os-partner:20840
TEST=Run "intel_reg_read 0x45270" command on a falco. It should come back
with "0x45270 : 0x1C00A7".

Change-Id: I9eaae4bc33b391302aa6b3b9a0c86b01a8da3e00
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61667
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 56e65f9..3bf22aa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2335,7 +2335,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
 	/* The WM are computed with base on how long it takes to fill a single
 	 * row at the given clock rate, multiplied by 8.
 	 * */
-	linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
+	linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, target_clock);
 	ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
 					 intel_ddi_get_cdclk_freq(dev_priv));
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drivers: i915: intel_hdmi deleted unused variable

[james.ausmus]

From: Paul Taysom <taysom@chromium.org>

drivers/gpu/drm/i915/intel_hdmi.c:785:27: warning: unused variable 'adjusted_mode' [-Wunused-variable]

Deleted unused variable, adjusted_mode.

BUG=chromium:237705
TEST=compile kernel and look for warnings.
Signed-off-by: Paul Taysom <taysom@chromium.org>

Change-Id: I9407b3a54ebba0a7fba0f6e0d1db75ca45cd8acd
Reviewed-on: https://gerrit.chromium.org/gerrit/61996
Tested-by: Paul Taysom <taysom@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Commit-Queue: Paul Taysom <taysom@chromium.org>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 0a27ec1..3ad1050 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -782,7 +782,6 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 {
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	struct drm_device *dev = encoder->base.dev;
-	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 
 	if (intel_hdmi->color_range)
 		pipe_config->limited_color_range = true;
-- 
1.8.3.2

[PATCH] CHROMIUM: drm/i915: Increase the wakeup up delay for PPT

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

This is basically increasing the delay added by commit:

commit 1d20c4fb51f18461f385ab7f039f695d37b15958
Author: Stéphane Marchesin <marcheu@chromium.org>
Date:   Wed Jun 26 15:17:11 2013 -0700

    CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays

As it seems the previous delay wasn't enough.

BUG=chrome-os-partner:21306
TEST=still works on parrot, but couldn't repro the original bug

Change-Id: I08d79f41ce1ddf0b6bcd0c620f19f7eb6dbe86c0
Reviewed-on: https://gerrit.chromium.org/gerrit/63399
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Reviewed-by: Mohammed Habibulla <moch@chromium.org>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c933bfa..d13e3a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4837,10 +4837,10 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
 	/*
 	 * On resume, the PPT PCH doesn't seem to work right away, and
 	 * sometimes ignores register read/writes until it's completely up.
-	 * Waiting 30ms seems to be long enough to avoid this.
+	 * Waiting 60ms seems to be long enough to avoid this.
 	 */
 	if (dev_priv->pch_id == INTEL_PCH_PPT_DEVICE_ID_TYPE)
-		msleep(30);
+		msleep(60);
 
 }
 
-- 
1.8.3.2

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[PATCH] CHROMIUM: drm/i915: Don't load boot context at init time on SNB

[james.ausmus]

From: Stéphane Marchesin <marcheu@chromium.org>

This breaks video decode on SNB, so let's not do it.

BUG=chromium:260836
TEST=by hand, video works after resume

Change-Id: I059b022ba1379599f219ad0828e3b4d0e0195f0b
Reviewed-on: https://gerrit.chromium.org/gerrit/65431
Tested-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Ilja H. Friedel <ihf@chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Antoine Labour <piman@chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 73f35cb..4d63d53 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4268,8 +4268,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
 
 	/* WaMbcDriverBootEnable */
-	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
-		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
+	/* This breaks video on resume */
+/*	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
+		   GEN6_MBCTL_ENABLE_BOOT_FETCH);*/
 
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
-- 
1.8.3.2

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Re: [RFC] drm/i915: Non-upstream ChromeOS patches from 3.8

[Daniel Vetter]

On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.ausmus@intel.com wrote:
> Hello All-
> 
> I'm trying to determine if the ChromeOS-only patches being carried by 
> Google still make sense and are the right way to do things in the 3.11+
> world, and Jesse asked me to forward the patches to the list for evaluation
> and potential upstreaming.

I've quickly read through the pile here and there's a few things we need
to look at. But one thing which makes assessing the patches here a bit a
pain is that often there's a fixup later on again. E.g. rc6 is tuned in
about 5-6 different patches. There's also a bunch of patches to fix up
warnings introduced in earlier ones

So can you please go through this and squash in the fixups into the
relevant original patches and resubmit? Please keep the commit messages
around in case there's interesting stuff in there like when a tuning value
changes again.

Thanks, Daniel

> 
> Thanks!
> 
> -James
> 
> 
> [PATCH] drm/i915: Only apply the adaptive backlight modulation when
> [PATCH] drm/i915: Add a try limit to avoid infinite loops
> [PATCH] drm/i915: Add a timeout to a potentially infinite loop
> [PATCH] i915: Use 120MHz LVDS SSC clock for gen5/gen6/gen7
> [PATCH] drm/i915: Make intel_dp_aux_native_read timeout
> [PATCH] drm/i915: Honor i915_min_freq post resume
> [PATCH] Wake up DP sinks for DPCD read-based detection.
> [PATCH] Restrict DP sink wake up to non-EDP.
> [PATCH] Fix display underruns on Pineview with 2048x1280 VGA display.
> [PATCH] CHROMIUM: drivers: i915: select non-alternate SSC frequency
> [PATCH] CHROMIUM: drivers: i915: Default backlight PWM frequency
> [PATCH] CHROMIUM: enable i915 power-saving render C-state 6 by
> [PATCH] CHROMIUM: drm/i915: Enable LVDS downclocking
> [PATCH] CHROMIUM: drm/i915: Reeneable FB compression and semaphores
> [PATCH] CHROMIUM: drm/i915: Adjust the down threshold.
> [PATCH] CHROMIUM: drm/i915: Adjust the RPS thresholds
> [PATCH] CHROMIUM: drm/i915: Move the backlight accessor functions in
> [PATCH] CHROMIUM: drm/i915: Add backlight support for Link
> [PATCH] CHROMIUM: drm/i915: set enable_rc6 to per-chip default.
> [PATCH] CHROMIUM: gpu: i915: optimize vblank timeout
> [PATCH] CHROMIUM: i915: Allow 0 level when turning on backlight.
> [PATCH] CHROMIUM: drm/i915: Check the current edp backlight state
> [PATCH] CHROMIUM: drm/i915: Workaround disappearing AVI Infoframe on
> [PATCH] CHROMIUM: Partial revert of
> [PATCH] CHROMIUM: drm/i915: bounds check execbuffer relocations
> [PATCH] CHROMIUM: drm/i915: Improve RC6p stability
> [PATCH] CHROMIUM: drm/i915/intel_i2c: enable 400kHz GMBUS for
> [PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for cyapa
> [PATCH] CHROMIUM: drm/i915/intel_i2c: Allow 400khz for atmel mxt bl
> [PATCH] CHROMIUM: drm/i915: fix resume
> [PATCH] CHROMIUM: drm/i915: Fix warning
> [PATCH] CHROMIUM: drm/i915: Initialize the backlight when reported
> [PATCH] CHROMIUM: drm/i915: Don't evict bound object in the shrinker
> [PATCH] CHROMIUM: drm/i915/intel_drv: reduce wait_for polling time
> [PATCH] CHROMIUM: drm/i915: tune the RC6 timeout for stability
> [PATCH] CHROMIUM: drm/i915: repin bound framebuffers on resume
> [PATCH] CHROMIUM: i915: fix max backlight in normal mode
> [PATCH] CHROMIUM: drm/i915: Tune the rc6 value again
> [PATCH] CHROMIUM: drm/i915: Work around PPT chipsets wakeup delays
> [PATCH] CHROMIUM: drm/i915: set lower RC6_THRESHOLD for HSW
> [PATCH] CHROMIUM: drm/i915: set linetime WM based on target_clock
> [PATCH] CHROMIUM: drivers: i915: intel_hdmi deleted unused variable
> [PATCH] CHROMIUM: drm/i915: Increase the wakeup up delay for PPT
> [PATCH] CHROMIUM: drm/i915: Don't load boot context at init time on
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH] CHROMIUM: enable i915 power-saving render C-state 6 by default.

[Chris Wilson]

On Thu, Aug 15, 2013 at 05:30:37PM -0700, james.ausmus@intel.com wrote:
> From: Todd Broch <tbroch@chromium.org>
> 
> BUG=chrome-os-partner:6768
> TEST=manual,
> - boot kernel
> 1. cat /sys/module/i915/parameters/i915_enable_rc6
>   - should equal 1
> 2. start powertop, goto 'Idle Stats' tab
>   - make sure that the Package c-states (C6, C7) are entered at some
>     non-trivial percentage when system is idle
> 
> Signed-off-by: Todd Broch <tbroch@chromium.org>
> Change-Id: Ib557a14e3cf20b55a6670808e681ef21b1e0ed1b
> Reviewed-on: https://gerrit.chromium.org/gerrit/12280
> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>

Drop this patch. This is incorrect against upstream.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] CHROMIUM: drm/i915: Adjust the down threshold.

[Chris Wilson]

On Thu, Aug 15, 2013 at 05:30:40PM -0700, james.ausmus@intel.com wrote:
> From: Stéphane Marchesin <marcheu@chromium.org>
> 
> The thresholds for GPU reclocking are highly asymetrical. This creates an
> interesting phenomenon on Chrome startup where the clock ramps up very
> quickly, and then the blinking cursor is enough to keep it up. Obviously
> having the max GPU clock on the login screen is very bad for thermals.
> 
> With this change, the clock goes back to its minimum frequency after a couple
> of seconds.

You can drop the RPS changes as Stéphane has been feeding these back
once he found (semi?) stable values.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] Wake up DP sinks for DPCD read-based detection.

[Chris Wilson]

On Thu, Aug 15, 2013 at 05:30:32PM -0700, james.ausmus@intel.com wrote:
>  static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  				  enum pipe *pipe)
>  {
> @@ -2330,6 +2336,12 @@ intel_dp_detect(struct drm_connector *connector, bool force)
>  
>  	intel_dp->has_audio = false;
>  
> +	/* Ensure the sink is awake for DPCD/EDID reads. */

I would try using the force parameter to return the last known status to
avoid the extra busy work.

> +	if (connector->dpms != DRM_MODE_DPMS_ON) {
> +		/* Bypass DPCD check, since we obtain it during detection. */
> +		intel_dp_do_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> +	}
> +
>  	if (HAS_PCH_SPLIT(dev))
>  		status = ironlake_dp_detect(intel_dp);
>  	else
> @@ -2339,8 +2351,11 @@ intel_dp_detect(struct drm_connector *connector, bool force)
>  			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
>  	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
>  
> -	if (status != connector_status_connected)
> +	if (status != connector_status_connected) {
> +		if (connector->dpms != DRM_MODE_DPMS_ON)
> +			intel_dp_do_sink_dpms(intel_dp, connector->dpms);
>  		return status;
> +	}
>  
>  	intel_dp_probe_oui(intel_dp);
>  
> @@ -2356,6 +2371,11 @@ intel_dp_detect(struct drm_connector *connector, bool force)
>  
>  	if (intel_encoder->type != INTEL_OUTPUT_EDP)
>  		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> +
> +	/* Restore the sink state */
> +	if (connector->dpms != DRM_MODE_DPMS_ON)
> +		intel_dp_do_sink_dpms(intel_dp, connector->dpms);
> +
>  	return connector_status_connected;
>  }

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] CHROMIUM: drm/i915: Reeneable FB compression and semaphores for kernel 3.2

[Chris Wilson]

On Thu, Aug 15, 2013 at 05:30:39PM -0700, james.ausmus@intel.com wrote:
> From: Simon Que <sque@chromium.org>
> 
> marcheu added these changes in kernel 3.0:
>  https://gerrit.chromium.org/gerrit/12367
>  https://gerrit.chromium.org/gerrit/12368
> 
> They were undone in kernel 3.2.  This patch restores them.

They were disabled with good reason.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: Add a try limit to avoid infinite loops

[Chris Wilson]

On Thu, Aug 15, 2013 at 05:30:27PM -0700, james.ausmus@intel.com wrote:
> From: Chris Wolfe <cwolfe@chromium.org>
> 
> Unfortunately some combinations of hardware seem to generate successful
> communications on the aux channel, which always report deferred. As a
> result native_write can wind up in an infinite loop.
> 
> This hack adds a large (~10ms) retry limit to avoid a kernel panic,
> while hopefully minimizing the impact on working hardware.
> 
> Signed-off-by: cwolfe@chromium.org
> 
> BUG=chromium-os:34840
> TEST=Manually connect DP to VGA adapter to problem system. Added display
>      powers up and works normally, rather than black screen and reboot.
> 
> Change-Id: Ib1b0001ca8004e65c9c5e353dbdb5e252fd88438
> Reviewed-on: https://gerrit.chromium.org/gerrit/34203
> Commit-Ready: Chris Wolfe <cwolfe@chromium.org>
> Reviewed-by: Chris Wolfe <cwolfe@chromium.org>
> Tested-by: Chris Wolfe <cwolfe@chromium.org>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e5d16bc..ac7d610 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -491,6 +491,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
>  	uint8_t	msg[20];
>  	int msg_bytes;
>  	uint8_t	ack;
> +	int try;
>  
>  	intel_dp_check_edp(intel_dp);
>  	if (send_bytes > 16)
> @@ -501,7 +502,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
>  	msg[3] = send_bytes - 1;
>  	memcpy(&msg[4], send, send_bytes);
>  	msg_bytes = send_bytes + 4;
> -	for (;;) {
> +	for (try = 0; try < 100; try++) {
>  		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
>  		if (ret < 0)
>  			return ret;
> @@ -512,6 +513,10 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
>  		else
>  			return -EIO;
>  	}
> +	if (try == 100) {
> +		DRM_ERROR("too many retries, giving up\n");
> +		return -EREMOTEIO;
> +	}

If we break out here, we need to reset the hw somewhere as it will still
have the last command in the out queue.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [RFC] drm/i915: Non-upstream ChromeOS patches from 3.8

[Jani Nikula]

On Fri, 16 Aug 2013, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.ausmus@intel.com wrote:
>> Hello All-
>> 
>> I'm trying to determine if the ChromeOS-only patches being carried by 
>> Google still make sense and are the right way to do things in the 3.11+
>> world, and Jesse asked me to forward the patches to the list for evaluation
>> and potential upstreaming.
>
> I've quickly read through the pile here and there's a few things we
> need to look at.

Ditto, and agreed.

> But one thing which makes assessing the patches here a bit a pain is
> that often there's a fixup later on again.

Another pain is that sometimes the fixup is first, i.e. the series does
not seem to be in the right order.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center

Re: [RFC] drm/i915: Non-upstream ChromeOS patches from 3.8

[Ausmus, James]

[-- Attachment #1.1: Type: text/plain, Size: 1390 bytes --]

On Fri, Aug 16, 2013 at 1:15 AM, Jani Nikula <jani.nikula@linux.intel.com>
wrote:
>
> On Fri, 16 Aug 2013, Daniel Vetter <daniel@ffwll.ch> wrote:
> > On Thu, Aug 15, 2013 at 05:30:25PM -0700, james.ausmus@intel.com wrote:
> >> Hello All-
> >>
> >> I'm trying to determine if the ChromeOS-only patches being carried by
> >> Google still make sense and are the right way to do things in the 3.11+
> >> world, and Jesse asked me to forward the patches to the list for
evaluation
> >> and potential upstreaming.
> >
> > I've quickly read through the pile here and there's a few things we
> > need to look at.
>
> Ditto, and agreed.
>
> > But one thing which makes assessing the patches here a bit a pain is
> > that often there's a fixup later on again.
>
> Another pain is that sometimes the fixup is first, i.e. the series does
> not seem to be in the right order.

One of the issues is that it's not truly a series, but rather individual
patches
dating back through 2011 - I thought I had gotten git-send-email to push
them
out in chronological order, but maybe I was less successful than I thought.
:)

I'll see what I can do in regards to squishing some of these down - I have
fairly
limited knowledge when it comes to the i915 driver, so it may not end up
perfect, but I'll give it a go. :)

Thanks!

-James


>
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Technology Center

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