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bh=Yzsm7UcLWz95w7mf2csUHMiUJrt8gEY4jLejuhdiuAM=; b=TnqxEC8om1vFtcEub3V/hkQWm1SBJYORapt54lhZfyc8VpvxaKlWoT/AP5A82neKZGZrzA P/1iSrfE1Yf+O8OJOQUbtHcvABWj2WNUpKdVe3pBwUL1aP1XcFZlef17BmegzDl1yKfuvV yUKT+fDCcr1RV4nxqc6OzVFANsub2kAmba3+Av/8HezTYdNhjhnLGbCoc2KK1Fg35ywZZf wtpstfHAPYAtF4uYod7oKQIfRYfGP5eozhv1hQfSr0Pou/wWHDSvgMWqZ9d+/zSSwacz9S hrNaBr2GD2Wt4uc2m5jA+sndXOso0K0gEf7Ec+SNaYaOnJUli/zxWNHVjzfZIg== From: Miquel Raynal To: James Hilliard Cc: Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Richard Genoud , Masahiro Yamada , Boris Brezillon , Brian Norris , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v6 01/18] mtd: rawnand: sunxi: drain interrupts before reusing the completion In-Reply-To: (James Hilliard's message of "Mon, 12 Oct 2026 13:17:23 -0600") References: <20260914-submit-sunxi-nand-vendor-oob-layout-v1-v6-0-2fb084fe0751@gmail.com> <20260914-submit-sunxi-nand-vendor-oob-layout-v1-v6-1-2fb084fe0751@gmail.com> <8733ua23xs.fsf@bootlin.com> <877bjmzqkr.fsf@bootlin.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Mon, 12 Oct 2026 22:53:22 +0200 Message-ID: <87pkxey725.fsf@bootlin.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 >> >> commit log, I now disagree with the first part of: >> >> >> >> >The old handler can also complete the new wait or restore an obsolet= e interrupt mask. >> >> >> >> "complete the new wait"? I don't see how a stale handler completes the >> >> next wait given the handler is a hard IRQ and the interrupt enable >> >> register is cleared on timeout. >> > >> > The case I had in mind is an already-running handler on another CPU: >> > >> > CPU 0: Read st and ien for operation A. >> > CPU 1: Time out operation A, mask/acknowledge its interrupts, >> > then eventually reinitialize the completion for operation B. >> > CPU 0: Call complete() based on the saved st and ien from operation A. >> >> For this to fire, the hard IRQ handler on CPU0 would have to be stopped >> between reading st/ien and calling complete() long enough to span: >> - A's timeout >> - A's cleanup >> - B's wait being rearmed >> On this hardware, how is this reachable? > > CONFIG_PREEMPT_RT provides a concrete mechanism. The driver requests this > IRQ with flags =3D 0, without IRQF_NO_THREAD, so the handler is > forced-threaded. A higher-priority task can preempt that IRQ thread > after it reads st/ien: That argument only appears in this reply. It is not in the commit log nor in the diff, both of which reason about a hard IRQ, no? I'll happily take the PREEMPT_RT case into account: in that configuration the case is reachable, but it reads as a justification added after the fact. Then, I'm curious to know how the AI justifies the use of disable_irq() as the RT-appropriate choice: doesn't it block without a timeout on the very IRQ thread the scenario relies on being starved (and gives no priority inheritance)? Thanks, Miqu=C3=A8l