From: Marc Zyngier <maz@kernel.org>
To: Fuad Tabba <tabba@google.com>
Cc: sashiko-reviews@lists.linux.dev, Oliver Upton <oupton@kernel.org>,
kvmarm@lists.linux.dev, Will Deacon <will@kernel.org>
Subject: Re: [PATCH] KVM: arm64: Sync SPSR_EL1 when injecting an exception into a pVM
Date: Sun, 14 Jun 2026 09:49:23 +0100 [thread overview]
Message-ID: <87pl1t8q24.wl-maz@kernel.org> (raw)
In-Reply-To: <CA+EHjTyFFf__9iGFAyAkechiX+gaiK9ksdfgxLSFe8RcAY=HGA@mail.gmail.com>
On Fri, 12 Jun 2026 14:19:10 +0100,
Fuad Tabba <tabba@google.com> wrote:
>
> On Fri, 12 Jun 2026 at 12:50, <sashiko-bot@kernel.org> wrote:
> >
> > Could this cause the guest kernel's exception decoding logic to fail or
> > panic?
>
> You're right -- the architecture mandates setting IL here. Like you
> said, this is pre-existing, and I'll submit a separate patch to fix
> it. But first, Marc: was there a specific reason for not setting it,
> or is it just an omission?
Just a plain bug. The normal KVM code is usually careful to construct
the new ESR based on the source of the exception, meaning that we
always convert ESR_EL2 into ESR_EL1, and propagate IL amongst other
things. This is obviously not the case here.
It'd be worth auditing the rest of the code and make sure this is the
only case of IL not being correctly set.
Thanks,
M.
--
Jazz isn't dead. It just smells funny.
next prev parent reply other threads:[~2026-06-14 8:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-12 11:34 [PATCH] KVM: arm64: Sync SPSR_EL1 when injecting an exception into a pVM Fuad Tabba
2026-06-12 11:50 ` sashiko-bot
2026-06-12 13:19 ` Fuad Tabba
2026-06-14 8:49 ` Marc Zyngier [this message]
2026-06-14 10:36 ` Fuad Tabba
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