From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C436EFCC9D1 for ; Tue, 10 Mar 2026 07:05:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vzr9j-0000PR-Su; Tue, 10 Mar 2026 03:05:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vzr9i-0000PA-Eh for qemu-arm@nongnu.org; Tue, 10 Mar 2026 03:05:26 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vzr9g-0000Vc-0Z for qemu-arm@nongnu.org; Tue, 10 Mar 2026 03:05:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1773126322; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=dOWsMxDffEU5sonTHWg6k8c6XF/rLnGiTdq6/9hDcI4=; b=dxSo3TJ9oBOI8GAwFBu+0/PsBwS0YXTSjP9MtPLqMzL/azUsrmJa0j9PsJN2GjrcVmWE3v VulAJM6vd1zotkqBu/wDb8SIEAXbWEAz63Hxt4pDsAMiWaJyK3OUyAmW3vAYQkA8RXu9ys 4yMUxliRaH/CNXb5/qhJtketPpvCdIM= Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-483-HKQBG9fTPK2O7aF3QzAIbw-1; Tue, 10 Mar 2026 03:05:19 -0400 X-MC-Unique: HKQBG9fTPK2O7aF3QzAIbw-1 X-Mimecast-MFC-AGG-ID: HKQBG9fTPK2O7aF3QzAIbw_1773126317 Received: from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 535CE19560B7; Tue, 10 Mar 2026 07:05:17 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.45.242.12]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3AC4F30002D2; Tue, 10 Mar 2026 07:05:16 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 75DC221E681B; Tue, 10 Mar 2026 08:05:13 +0100 (CET) From: Markus Armbruster To: Nathan Chen Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Yi Liu , Eric Auger , Zhenzhong Duan , Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Daniel P . =?utf-8?Q?Berrang=C3=A9?= , Alex Williamson , =?utf-8?Q?C=C3=A9dric?= Le Goater , Eric Blake Subject: Re: [RFC PATCH 2/8] hw/arm/smmuv3-accel: Introduce _AUTO support for ATS In-Reply-To: <20260309192119.870186-3-nathanc@nvidia.com> (Nathan Chen's message of "Mon, 9 Mar 2026 12:21:13 -0700") References: <20260309192119.870186-1-nathanc@nvidia.com> <20260309192119.870186-3-nathanc@nvidia.com> Date: Tue, 10 Mar 2026 08:05:13 +0100 Message-ID: <87pl5cnp06.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 X-Mimecast-MFC-PROC-ID: sF6pLG9bxLhJOOwqIZX5TeGpQxKAjoGGx2kuxoo9iEg_1773126317 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Nathan Chen writes: > From: Nathan Chen > > Allow accelerated SMMUv3 Address Translation Services support property > to be derived from host IOMMU capabilities. Derive host values using > IOMMU_GET_HW_INFO, retrieving ATS capability from IDR0. > > Set the default value of ATS to auto. The default for ATS support used > to be set to off, but we change it to match what the host IOMMU > properties report. > > Add a "ats-enabled" read-only property for smmuv3 to address an > expected bool for the "ats" property in iort_smmuv3_devices(). > > Signed-off-by: Nathan Chen > --- > hw/arm/smmuv3-accel.c | 25 +++++++++++++++++++++++-- > hw/arm/smmuv3.c | 12 ++++++++++-- > hw/arm/virt-acpi-build.c | 2 +- > include/hw/arm/smmuv3.h | 2 +- > 4 files changed, 35 insertions(+), 6 deletions(-) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 617629bacd..8fec335557 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -52,6 +52,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, PCIDevice *pdev, > return; > } > > + /* Update ATS if auto from info */ > + if (s->ats == ON_OFF_AUTO_AUTO) { > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, > + FIELD_EX32(info->idr[0], IDR0, ATS)); > + } > + > accel->auto_finalised = true; > } > > @@ -124,6 +130,13 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, > smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); > return false; > } > + /* Check ATS value opted is compatible with Host SMMUv3 */ > + if (FIELD_EX32(info->idr[0], IDR0, ATS) < > + FIELD_EX32(s->idr[0], IDR0, ATS)) { > + error_setg(errp, "Host SMMUv3 doesn't support Address Translation" > + " Services"); > + return false; > + } > > /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ > if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) != > @@ -844,8 +857,12 @@ void smmuv3_accel_idr_override(SMMUv3State *s) > /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */ > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); > > - /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ > - s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); > + /* Only override ATS if user explicitly set ON or OFF */ > + if (s->ats == ON_OFF_AUTO_ON) { > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1); > + } else if (s->ats == ON_OFF_AUTO_OFF) { > + s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 0); > + } > > /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ > if (s->oas == SMMU_OAS_48BIT) { > @@ -923,4 +940,8 @@ void smmuv3_accel_init(SMMUv3State *s) > s->s_accel = g_new0(SMMUv3AccelState, 1); > bs->iommu_ops = &smmuv3_accel_ops; > smmuv3_accel_as_init(s); > + > + if (s->ats == ON_OFF_AUTO_AUTO) { > + s->s_accel->auto_mode = true; > + } > } > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 068108e49b..197ba7c77b 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -317,6 +317,12 @@ static void smmuv3_init_id_regs(SMMUv3State *s) > smmuv3_accel_idr_override(s); > } > > +static bool get_ats_enabled(Object *obj, Error **errp) > +{ > + SMMUv3State *s = ARM_SMMUV3(obj); > + return FIELD_EX32(s->idr[0], IDR0, ATS); > +} > + > static void smmuv3_reset(SMMUv3State *s) > { > s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); > @@ -1971,7 +1977,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp) > error_setg(errp, "ril can only be disabled if accel=on"); > return false; > } > - if (s->ats) { > + if (s->ats == ON_OFF_AUTO_ON) { > error_setg(errp, "ats can only be enabled if accel=on"); > return false; > } > @@ -2128,7 +2134,7 @@ static const Property smmuv3_properties[] = { > DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), > /* RIL can be turned off for accel cases */ > DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), > - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), > + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), Is property "ats" accessible via QMP or JSON command line? If yes, this is an incompatible change: JSON values false and true no longer work. > DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), > DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), > }; > @@ -2153,6 +2159,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data) > dc->hotpluggable = false; > dc->user_creatable = true; > > + object_class_property_add_bool(klass, "ats-enabled", get_ats_enabled, NULL); > + > object_class_property_set_description(klass, "accel", > "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " > "configured in nested mode for vfio-pci dev assignment"); > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index 719d2f994e..6c77fc5f6a 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaque) > > bus = PCI_BUS(object_property_get_link(obj, "primary-bus", &error_abort)); > sdev.accel = object_property_get_bool(obj, "accel", &error_abort); > - sdev.ats = object_property_get_bool(obj, "ats", &error_abort); > + sdev.ats = object_property_get_bool(obj, "ats-enabled", &error_abort); > pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); > sbdev = SYS_BUS_DEVICE(obj); > sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0); > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index 26b2fc42fd..2ca49ded36 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -70,7 +70,7 @@ struct SMMUv3State { > uint64_t msi_gpa; > Error *migration_blocker; > bool ril; > - bool ats; > + OnOffAuto ats; > uint8_t oas; > uint8_t ssidsize; > };