Re: [PATCH dovetail 6.11 v2 0/3] RISC-V: IRQ pipelining core

[Philippe Gerum <rpm@xenomai.org>]

Hi,

I started a Dovetail branch [1] for the RISC-V port, forward porting
your series (since it's SMP-enabled already) to 6.12-rc6. The code was
split in few more patches, including a couple of fixes we need as
well. The latter may be folded into the core pipeline support later
on. From that point, we could then pick the upper layer of the Dovetail
code already ported by Shanmu in order to enable EVL on top.

I recommend enabling the following switches when working on this port,
so that we can detect any issue with the virtual interrupt state:

CONFIG_PROVE_LOCKING
CONFIG_PREEMPT_RT
CONFIG_DEBUG_PREEMPT
CONFIG_RISCV_ISA_V_PREEMPTIVE

Here we go, so far:

root@homelab-qemu-riscv64:~# uname -a
Linux homelab-qemu-riscv64 6.12.0-rc6-00145-gb4167b69ed0e #20 SMP PREEMPT_RT IRQ_PIPELINE Mon Nov  4 10:26:04 CET 2024 riscv64 GNU/Linux

PS: I switched from RISC-V: to riscv: in the shortlogs to follow the
(most) common scheme used so far, which is likely to reuse the name of
the architecture folder.

[1] https://source.denx.de/Xenomai/linux-dovetail/-/tree/wip/dovetail-riscv?ref_type=heads

Tobias Schaffner <tobias.schaffner@siemens.com> writes:

> Hi all,
>
> This introduces IRQ pipelining for RISC-V into Dovetail. The patches
> are on top of v6.11-dovetail-rebase. Feel free to ask for other targets
> if needed.
>
> I thought about splitting the patch up into smaller parts, but decided
> to stick to the structure of the analogous patches of the other
> architectures. Maybe this will make the rebasing process easier.
>
> Testing was done in QEMU with IRQ pipeline torture tests, both with and
> without SMP enabled.
>
> Changes since v1:
> * Removed some dovetail specific changes. These will be readded in a
>   later dovetail patch series. Thanks for the kind review @rpm!
> * Added a patch that guards _TIF_RETUSER with an CONFIG_DOVETAIL ifdef
>   to allow building with IRQ pipelining but without dovetail being
>   implemented.
> * Fix unneeded reordering in riscv irqflags.h to make the diff nicer.
>
> Tobias Schaffner (3):
>   dovetail: Guard _TIF_RETUSER with CONFIG_DOVETAIL
>   clocksource/timer-riscv: irq_pipeline: enable pipelined clock events
>   RISC-V: irq_pipeline: add IRQ pipelining core
>
>  arch/riscv/Kconfig                         |   1 +
>  arch/riscv/include/asm/irq_pipeline.h      | 143 +++++++++++++++++++++
>  arch/riscv/include/asm/irqflags.h          |  25 ++--
>  arch/riscv/include/asm/thread_info.h       |   8 ++
>  arch/riscv/kernel/Makefile                 |   1 +
>  arch/riscv/kernel/irq_pipeline.c           |  26 ++++
>  arch/riscv/kernel/smp.c                    |  93 +++++++++++++-
>  arch/riscv/kernel/smpboot.c                |   2 +-
>  arch/riscv/kernel/traps.c                  |  51 +++++++-
>  arch/riscv/mm/fault.c                      |  83 ++++++++++--
>  drivers/clocksource/timer-riscv.c          |  11 +-
>  drivers/irqchip/irq-riscv-aplic-direct.c   |   3 +-
>  drivers/irqchip/irq-riscv-aplic-msi.c      |   3 +-
>  drivers/irqchip/irq-riscv-imsic-platform.c |   3 +-
>  drivers/irqchip/irq-riscv-intc.c           |   2 +
>  drivers/irqchip/irq-sifive-plic.c          |   3 +-
>  include/linux/entry-common.h               |   4 +-
>  17 files changed, 420 insertions(+), 42 deletions(-)
>  create mode 100644 arch/riscv/include/asm/irq_pipeline.h
>  create mode 100644 arch/riscv/kernel/irq_pipeline.c

-- 
Philippe.