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Fri, 26 May 2023 13:26:01 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.91]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C7FB3C15612; Fri, 26 May 2023 13:26:00 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 9E88A21E692E; Fri, 26 May 2023 15:25:59 +0200 (CEST) From: Markus Armbruster To: Jonathan Cameron Cc: , Michael Tsirkin , Fan Ni , , , Ira Weiny , Michael Roth , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Dave Jiang , Daniel P . =?utf-8?Q?Berrang=C3=A9?= , Eric Blake , Mike Maslenkin , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Thomas Huth Subject: Re: [PATCH v7 6/7] hw/cxl/events: Add injection of DRAM events References: <20230522150947.11546-1-Jonathan.Cameron@huawei.com> <20230522150947.11546-7-Jonathan.Cameron@huawei.com> Date: Fri, 26 May 2023 15:25:59 +0200 In-Reply-To: <20230522150947.11546-7-Jonathan.Cameron@huawei.com> (Jonathan Cameron's message of "Mon, 22 May 2023 16:09:46 +0100") Message-ID: <87pm6n8brs.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Jonathan Cameron writes: > Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event > provides information related to DRAM devices. > > Example injection command in QMP: > > { "execute": "cxl-inject-dram-event", > "arguments": { > "path": "/machine/peripheral/cxl-mem0", > "log": "informational", > "flags": 1, > "dpa": 1000, > "descriptor": 3, > "type": 3, > "transaction-type": 192, > "channel": 3, > "rank": 17, > "nibble-mask": 37421234, > "bank-group": 7, > "bank": 11, > "row": 2, > "column": 77, > "correction-mask": [33, 44, 55,66] > }} > > Reviewed-by: Ira Weiny > Signed-off-by: Jonathan Cameron > > --- > v7: Additional documentation, plus rename physaddr to dpa reduce > confusion > --- > qapi/cxl.json | 63 ++++++++++++++++++++ > include/hw/cxl/cxl_events.h | 23 +++++++ > hw/mem/cxl_type3.c | 116 ++++++++++++++++++++++++++++++++++++ > hw/mem/cxl_type3_stubs.c | 13 ++++ > 4 files changed, 215 insertions(+) > > diff --git a/qapi/cxl.json b/qapi/cxl.json > index 7700e26a0d..ce9adcbc55 100644 > --- a/qapi/cxl.json > +++ b/qapi/cxl.json > @@ -84,6 +84,69 @@ > '*channel': 'uint8', '*rank': 'uint8', > '*device': 'uint32', '*component-id': 'str' } } > > +## > +# @cxl-inject-dram-event: > +# > +# Inject an event record for a DRAM Event (CXL r3.0 8.2.9.2.1.2) Period at end of sentence, please. > +# This event type is reported via one of the event logs specified via > +# the log parameter. > +# > +# @path: CXL type 3 device canonical QOM path > +# > +# @log: Event log to add the event to > +# > +# @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event > +# Record Format, Event Record Flags for subfield definitions. > +# > +# @dpa: Device Physical Address (relative to @path device). Note lower > +# bits include some flags. See CXL r3.0 Table 8-44 DRAM Event > +# Record, Physical Address. > +# > +# @descriptor: Memory Event Descriptor with additional memory > +# event information. See CXL r3.0 Table 8-44 DRAM Event > +# Record, Memory Event Descriptor for bit definitions. > +# > +# @type: Type of memory event that occurred. See CXL r3.0 Table 8-44 > +# DRAM Event Record, Memory Event Type for possible values. > +# > +# @transaction-type: Type of first transaction that caused the event > +# to occur. See CXL r3.0 Table 8-44 DRAM Event > +# Record, Transaction Type for possible values. > +# > +# @channel: The channel of the memory event location. A channel is > +# an interface that can be independently accessed for a > +# transaction. > +# > +# @rank: The rank of the memory event location. A rank is a set of > +# memory devices on a channel that together execute a > +# transaction. > +# > +# @nibble-mask: Identify one or more nibbles that the error affects "Identifies", I think. > +# > +# @bank-group: Bank group of the memory event location, incorporating > +# a number of Banks. > +# > +# @bank: Bank of the memory event location. A single bank is accessed > +# per read or write of the memory. > +# > +# @row: Row address within the DRAM. > +# > +# @column: Column address within the DRAM. > +# > +# @correction-mask: Bits within each nibble. Used in order of bits set > +# in the nibble-mask. Up to 4 nibbles may be covered. Please format like # @flags: Event Record Flags. See CXL r3.0 Table 8-42 Common Event # Record Format, Event Record Flags for subfield definitions. # # @dpa: Device Physical Address (relative to @path device). Note # lower bits include some flags. See CXL r3.0 Table 8-44 DRAM # Event Record, Physical Address. # # @descriptor: Memory Event Descriptor with additional memory event # information. See CXL r3.0 Table 8-44 DRAM Event Record, Memory # Event Descriptor for bit definitions. # # @type: Type of memory event that occurred. See CXL r3.0 Table 8-44 # DRAM Event Record, Memory Event Type for possible values. # # @transaction-type: Type of first transaction that caused the event # to occur. See CXL r3.0 Table 8-44 DRAM Event Record, # Transaction Type for possible values. # # @channel: The channel of the memory event location. A channel is an # interface that can be independently accessed for a transaction. # # @rank: The rank of the memory event location. A rank is a set of # memory devices on a channel that together execute a transaction. # # @nibble-mask: Identifies one or more nibbles that the error affects # # @bank-group: Bank group of the memory event location, incorporating # a number of Banks. # # @bank: Bank of the memory event location. A single bank is accessed # per read or write of the memory. # # @row: Row address within the DRAM. # # @column: Column address within the DRAM. # # @correction-mask: Bits within each nibble. Used in order of bits # set in the nibble-mask. Up to 4 nibbles may be covered. to blend in with recent commit a937b6aa739 (qapi: Reformat doc comments to conform to current conventions). > +# > +# Since: 8.1 > +## > +{ 'command': 'cxl-inject-dram-event', > + 'data': { 'path': 'str', 'log': 'CxlEventLog', 'flags': 'uint8', > + 'dpa': 'uint64', 'descriptor': 'uint8', > + 'type': 'uint8', 'transaction-type': 'uint8', > + '*channel': 'uint8', '*rank': 'uint8', '*nibble-mask': 'uint32', > + '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32', > + '*column': 'uint16', '*correction-mask': [ 'uint64' ] > + }} > + > ## > # @cxl-inject-poison: > # With these tweaks Acked-by: Markus Armbruster [...]