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From: Marc Zyngier <maz@kernel.org>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 4/4] arm64: Document values for system registers on boot
Date: Thu, 08 Apr 2021 18:16:03 +0100	[thread overview]
Message-ID: <87pmz4ofxo.wl-maz@kernel.org> (raw)
In-Reply-To: <20210401180942.35815-5-broonie@kernel.org>

Hi Mark,

On Thu, 01 Apr 2021 19:09:42 +0100,
Mark Brown <broonie@kernel.org> wrote:
> 
> When booting require that the system registers available at or below the
> exception level the kernel is entered be initialised but do not specify
> what values should be used in the general case, creating some potential
> for issues if the kernel does not subsequently configure those registers
> explicitly (for example if they are not yet used by the kernel) or where
> their effects may create issues during early configuration.
> 
> Specify that where the architecture provides a reset value that value
> must be used.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  Documentation/arm64/booting.rst | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
> index 4fcc00add117..d49f568eb79d 100644
> --- a/Documentation/arm64/booting.rst
> +++ b/Documentation/arm64/booting.rst
> @@ -205,7 +205,9 @@ Before jumping into the kernel, the following conditions must be met:
>    All writable architected system registers at or below the exception
>    level where the kernel image will be entered must be initialised by
>    software at a higher exception level to prevent execution in an UNKNOWN
> -  state.
> +  state.  Where these architected system registers have reset values
> +  specified by the architecture they must be initialised to those values
> +  unless specified more specifically.
>  
>    - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
>      executing on.
> -- 
> 2.20.1
> 
> 

Is that always enforceable? Is that even desirable?

Take for example ICC_SRE_EL2.SRE. The reset value for that bit is
0. But it is extremely likely that the FW has set this bit to 1 in
order to be able to use interrupts with the sysreg interface. However,
as outlined in the GIC spec:

<quote>
If software changes this bit from 1 to 0, the results are UNPREDICTABLE.
</quote>

We could go and specify this one, but I fear there is a lot of things
we'd have to make explicit...

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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  reply	other threads:[~2021-04-08 17:22 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01 18:09 [PATCH v2 0/4] arm64: Booting clarifications and fine grained traps setup Mark Brown
2021-04-01 18:09 ` [PATCH v2 1/4] arm64: Document requirements for fine grained traps at boot Mark Brown
2021-04-08 17:00   ` Marc Zyngier
2021-04-01 18:09 ` [PATCH v2 2/4] arm64: Disable fine grained traps on boot Mark Brown
2021-04-08 17:00   ` Marc Zyngier
2021-04-01 18:09 ` [PATCH v2 3/4] arm64: Require that system registers at all visible ELs be initialized Mark Brown
2021-04-08 17:02   ` Marc Zyngier
2021-04-01 18:09 ` [PATCH v2 4/4] arm64: Document values for system registers on boot Mark Brown
2021-04-08 17:16   ` Marc Zyngier [this message]
2021-04-08 17:33     ` Mark Brown
2021-04-08 17:59 ` (subset) [PATCH v2 0/4] arm64: Booting clarifications and fine grained traps setup Catalin Marinas

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