From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C65FC3F2D1 for ; Thu, 5 Mar 2020 13:14:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09E142072A for ; Thu, 5 Mar 2020 13:14:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 09E142072A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A64956E1E0; Thu, 5 Mar 2020 13:14:29 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1FD426E1E0 for ; Thu, 5 Mar 2020 13:14:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2020 05:14:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,518,1574150400"; d="scan'208";a="234409698" Received: from gaia.fi.intel.com ([10.237.72.192]) by orsmga008.jf.intel.com with ESMTP; 05 Mar 2020 05:14:26 -0800 Received: by gaia.fi.intel.com (Postfix, from userid 1000) id 435505C1DDA; Thu, 5 Mar 2020 15:13:09 +0200 (EET) From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org In-Reply-To: <8736an58ql.fsf@gaia.fi.intel.com> References: <20200305073531.2594698-1-chris@chris-wilson.co.uk> <8736an58ql.fsf@gaia.fi.intel.com> Date: Thu, 05 Mar 2020 15:13:09 +0200 Message-ID: <87pndr3py2.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915/execlists: Enable timeslice on partial virtual engine dequeue X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Mika Kuoppala writes: > Chris Wilson writes: > >> If we stop filling the ELSP due to an incompatible virtual engine >> request, check if we should enable the timeslice on behalf of the queue. >> > > Leaves me pondering more of the why. > > So that on these boundaries also, the last rq gets subdued to > a timeslice and not get a free run? I got some confirmations on irc. Yes this for that. The commit message could be augmented on the why emphasis! > >> Signed-off-by: Chris Wilson >> --- >> drivers/gpu/drm/i915/gt/intel_lrc.c | 21 ++++++++++++++++----- >> 1 file changed, 16 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c >> index 5da86a40434c..954bd4797482 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c >> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c >> @@ -1802,6 +1802,20 @@ static void set_timeslice(struct intel_engine_cs *engine) >> set_timer_ms(&engine->execlists.timer, active_timeslice(engine)); >> } >> >> +static void start_timeslice(struct intel_engine_cs *engine, >> + struct i915_request *last) >> +{ >> + struct intel_engine_execlists *execlists = &engine->execlists; >> + >> + /* As we are returning early, update the hint from the queue */ >> + execlists->switch_priority_hint = >> + max(execlists->queue_priority_hint, >> + execlists->switch_priority_hint); Still not completely unclear how the all hints play together but the comment holds true, we bail out early. >> + >> + if (!execlists->timer.expires && need_timeslice(engine, last)) >> + set_timer_ms(&execlists->timer, timeslice(engine)); >> +} >> + >> static void record_preemption(struct intel_engine_execlists *execlists) >> { >> (void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++); >> @@ -1965,11 +1979,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) >> * Even if ELSP[1] is occupied and not worthy >> * of timeslices, our queue might be. >> */ >> - if (!execlists->timer.expires && >> - need_timeslice(engine, last)) >> - set_timer_ms(&execlists->timer, >> - timeslice(engine)); >> - >> + start_timeslice(engine, last); >> return; >> } >> } >> @@ -2004,6 +2014,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine) >> >> if (last && !can_merge_rq(last, rq)) { >> spin_unlock(&ve->base.active.lock); >> + start_timeslice(engine, last); >> return; /* leave this for another */ > > for another interrupt? For another veng. The comment might have already been augmented. Reviewed-by: Mika Kuoppala > -Mika > >> } >> >> -- >> 2.25.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx