From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 Date: Tue, 13 Oct 2015 16:10:19 +0300 Message-ID: <87pp0i52ys.fsf@intel.com> References: <1444244905-27894-1-git-send-email-ville.syrjala@linux.intel.com> <20151008081730.GZ3383@phenom.ffwll.local> <20151008081844.GS26517@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D8C36EA87 for ; Tue, 13 Oct 2015 06:08:49 -0700 (PDT) In-Reply-To: <20151008081844.GS26517@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?utf-8?B?U3lyasOkbMOk?= , Daniel Vetter Cc: Nick Bowler , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCAwOCBPY3QgMjAxNSwgVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4 LmludGVsLmNvbT4gd3JvdGU6Cj4gT24gVGh1LCBPY3QgMDgsIDIwMTUgYXQgMTA6MTc6MzBBTSAr MDIwMCwgRGFuaWVsIFZldHRlciB3cm90ZToKPj4gT24gV2VkLCBPY3QgMDcsIDIwMTUgYXQgMTA6 MDg6MjRQTSArMDMwMCwgdmlsbGUuc3lyamFsYUBsaW51eC5pbnRlbC5jb20gd3JvdGU6Cj4+ID4g RnJvbTogVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPj4g PiAKPj4gPiBXZSBhY2NpZGVudGFsbHkgbG9zdCB0aGUgaW5pdGlhbCBEUExMIHJlZ2lzdGVyIHdy aXRlIGluCj4+ID4gMWM0ZTAyNzQ2MTQ3IGRybS9pOTE1OiBGaXggRFZPIDJ4IGNsb2NrIGVuYWJs ZSBvbiA4MzBNCj4+ID4gCj4+ID4gVGhlICJ0aHJlZSB0aW1lcyBmb3IgbHVjayIgaGFjayBwcm9i YWJseSBzYXZlZCB1cyBmcm9tIGEgdG90YWwKPj4gPiBkaXNhc3Rlci4gQnV0IGFueXdheSwgYnJp bmcgdGhlIGluaXRpYWwgd3JpdGUgYmFjayBzbyB0aGF0IHRoZQo+PiA+IGNvZGUgYWN0dWFsbHkg bWFrZXMgc29tZSBzZW5zZS4KPj4gPiAKPj4gPiBDYzogc3RhYmxlQHZnZXIua2VybmVsLm9yZwo+ PiA+IENjOiBOaWNrIEJvd2xlciA8bmJvd2xlckBkcmFjb254LmNhPgo+PiBSZXBvcnRlZC1hbmQt dGVzdGVkLWJ5OiBOaWNrIEJvd2xlciA8bmJvd2xlckBkcmFjb254LmNhPgo+PiBSZWZlcmVuY2Vz OiBodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL2FyY2hpdmVzL2ludGVsLWdmeC8yMDE1LU9j dG9iZXIvMDc3NDYzLmh0bWwKPj4gCj4+ID4gU2lnbmVkLW9mZi1ieTogVmlsbGUgU3lyasOkbMOk IDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPj4gPiAtLS0KPj4gPiAgZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jIHwgMiArKwo+PiA+ICAxIGZpbGUgY2hhbmdlZCwg MiBpbnNlcnRpb25zKCspCj4+ID4gCj4+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2ludGVsX2Rpc3BsYXkuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXku Ywo+PiA+IGluZGV4IDE0N2U3MDAuLmY0ZmRmZjkgMTAwNjQ0Cj4+ID4gLS0tIGEvZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jCj4+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5 MTUvaW50ZWxfZGlzcGxheS5jCj4+ID4gQEAgLTE3NDMsNiArMTc0Myw4IEBAIHN0YXRpYyB2b2lk IGk5eHhfZW5hYmxlX3BsbChzdHJ1Y3QgaW50ZWxfY3J0YyAqY3J0YykKPj4gPiAgCQkJICAgSTkx NV9SRUFEKERQTEwoIWNydGMtPnBpcGUpKSB8IERQTExfRFZPXzJYX01PREUpOwo+PiAKPj4gRG9u J3Qgd2UgYWxzbyBuZWVkIGEgUE9TVElOR19SRUFEIGhlcmUgdG8gbWFrZSBzdXJlIHRoZSB0d28t c3RlcCAyeCBtb2RlCj4+IHNlcXVlbmNlIGlzIHN0aWxsIGZvbGxvd2VkPwo+Cj4gV2UgZG9uJ3Qg ZG8gd3JpdGUgY29tYmluaW5nIG9uIHJlZ2lzdGVycywgYW5kIHRoZXJlIGFyZSBubyBzaGFkb3cK PiByZWdpc3RlciB0eXBlIG9mIHRoaW5ncyB0byBjb25zaWRlciBpbiB0aGlzIGNhc2UgZWl0aGVy Lgo+Cj4+IAo+PiBXaXRoIHRoYXQgYWRkcmVzc2VkIFJldmlld2VkLWJ5OiBEYW5pZWwgVmV0dGVy IDxkYW5pZWwudmV0dGVyQGZmd2xsLmNoPgoKCkRhbmllbCwgYXJlIHlvdSBoYXBweSB3aXRoIHRo ZSByZXNwb25zZXMgYWJvdXQgcG9zdGluZyByZWFkcywgZm9yIGJvdGgKcGF0Y2hlcz8KCkJSLApK YW5pLgoKCgoKCj4+ID4gIAl9Cj4+ID4gIAo+PiA+ICsJSTkxNV9XUklURShyZWcsIGRwbGwpOwo+ PiA+ICsKPj4gPiAgCS8qIFdhaXQgZm9yIHRoZSBjbG9ja3MgdG8gc3RhYmlsaXplLiAqLwo+PiA+ ICAJUE9TVElOR19SRUFEKHJlZyk7Cj4+ID4gIAl1ZGVsYXkoMTUwKTsKPj4gPiAtLSAKPj4gPiAy LjQuOQo+PiA+IAo+PiA+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fCj4+ID4gSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdAo+PiA+IEludGVsLWdmeEBsaXN0cy5m cmVlZGVza3RvcC5vcmcKPj4gPiBodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4v bGlzdGluZm8vaW50ZWwtZ2Z4Cj4+IAo+PiAtLSAKPj4gRGFuaWVsIFZldHRlcgo+PiBTb2Z0d2Fy ZSBFbmdpbmVlciwgSW50ZWwgQ29ycG9yYXRpb24KPj4gaHR0cDovL2Jsb2cuZmZ3bGwuY2gKPgo+ IC0tIAo+IFZpbGxlIFN5cmrDpGzDpAo+IEludGVsIE9UQwo+IF9fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fCj4gSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdAo+IElu dGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKPiBodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Au b3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4CgotLSAKSmFuaSBOaWt1bGEsIEludGVsIE9w ZW4gU291cmNlIFRlY2hub2xvZ3kgQ2VudGVyCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vaW50ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com ([134.134.136.65]:40053 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932099AbbJMNI5 convert rfc822-to-8bit (ORCPT ); Tue, 13 Oct 2015 09:08:57 -0400 From: Jani Nikula To: Ville =?utf-8?B?U3lyasOkbMOk?= , Daniel Vetter Cc: Nick Bowler , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Restore lost DPLL register write on gen2-4 In-Reply-To: <20151008081844.GS26517@intel.com> References: <1444244905-27894-1-git-send-email-ville.syrjala@linux.intel.com> <20151008081730.GZ3383@phenom.ffwll.local> <20151008081844.GS26517@intel.com> Date: Tue, 13 Oct 2015 16:10:19 +0300 Message-ID: <87pp0i52ys.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Sender: stable-owner@vger.kernel.org List-ID: On Thu, 08 Oct 2015, Ville Syrjälä wrote: > On Thu, Oct 08, 2015 at 10:17:30AM +0200, Daniel Vetter wrote: >> On Wed, Oct 07, 2015 at 10:08:24PM +0300, ville.syrjala@linux.intel.com wrote: >> > From: Ville Syrjälä >> > >> > We accidentally lost the initial DPLL register write in >> > 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M >> > >> > The "three times for luck" hack probably saved us from a total >> > disaster. But anyway, bring the initial write back so that the >> > code actually makes some sense. >> > >> > Cc: stable@vger.kernel.org >> > Cc: Nick Bowler >> Reported-and-tested-by: Nick Bowler >> References: http://lists.freedesktop.org/archives/intel-gfx/2015-October/077463.html >> >> > Signed-off-by: Ville Syrjälä >> > --- >> > drivers/gpu/drm/i915/intel_display.c | 2 ++ >> > 1 file changed, 2 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> > index 147e700..f4fdff9 100644 >> > --- a/drivers/gpu/drm/i915/intel_display.c >> > +++ b/drivers/gpu/drm/i915/intel_display.c >> > @@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) >> > I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); >> >> Don't we also need a POSTING_READ here to make sure the two-step 2x mode >> sequence is still followed? > > We don't do write combining on registers, and there are no shadow > register type of things to consider in this case either. > >> >> With that addressed Reviewed-by: Daniel Vetter Daniel, are you happy with the responses about posting reads, for both patches? BR, Jani. >> > } >> > >> > + I915_WRITE(reg, dpll); >> > + >> > /* Wait for the clocks to stabilize. */ >> > POSTING_READ(reg); >> > udelay(150); >> > -- >> > 2.4.9 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Daniel Vetter >> Software Engineer, Intel Corporation >> http://blog.ffwll.ch > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center