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From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 03/11] drm/i915: Add support for pipe_bpp readout
Date: Fri, 13 Sep 2013 14:59:03 +0300	[thread overview]
Message-ID: <87ppsdlypk.fsf@intel.com> (raw)
In-Reply-To: <1378499348-4281-4-git-send-email-ville.syrjala@linux.intel.com>

On Fri, 06 Sep 2013, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On CTG+ read out the pipe bpp setting from hardware and fill it into
> pipe config. Also check it appropriately.
>
> v2: Don't do the pipe_bpp extraction inside the PCH only code block on
>     ILK+.
>     Avoid the PIPECONF read as we already have read it for the
>     PIPECONF_EANBLE check.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c     | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 060ea50..9305fb6 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1268,6 +1268,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
>  		flags |= DRM_MODE_FLAG_NVSYNC;
>  
>  	pipe_config->adjusted_mode.flags |= flags;
> +
> +	switch (temp & TRANS_DDI_BPC_MASK) {
> +	case TRANS_DDI_BPC_6:
> +		pipe_config->pipe_bpp = 18;
> +		break;
> +	case TRANS_DDI_BPC_8:
> +		pipe_config->pipe_bpp = 24;
> +		break;
> +	case TRANS_DDI_BPC_10:
> +		pipe_config->pipe_bpp = 30;
> +		break;
> +	case TRANS_DDI_BPC_12:
> +		pipe_config->pipe_bpp = 36;
> +		break;
> +	default:
> +		break;
> +	}
>  }
>  
>  static void intel_ddi_destroy(struct drm_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2aac205..35ad910 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4999,6 +4999,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>  	if (!(tmp & PIPECONF_ENABLE))
>  		return false;
>  
> +	if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> +		switch (tmp & PIPECONF_BPC_MASK) {
> +		case PIPECONF_6BPC:
> +			pipe_config->pipe_bpp = 18;
> +			break;
> +		case PIPECONF_8BPC:
> +			pipe_config->pipe_bpp = 24;
> +			break;
> +		case PIPECONF_10BPC:
> +			pipe_config->pipe_bpp = 30;
> +			break;
> +		default:
> +			break;
> +		}
> +	}
> +
>  	intel_get_pipe_timings(crtc, pipe_config);
>  
>  	i9xx_get_pfit_config(crtc, pipe_config);
> @@ -5899,6 +5915,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>  	if (!(tmp & PIPECONF_ENABLE))
>  		return false;
>  
> +	switch (tmp & PIPECONF_BPC_MASK) {
> +	case PIPECONF_6BPC:
> +		pipe_config->pipe_bpp = 18;
> +		break;
> +	case PIPECONF_8BPC:
> +		pipe_config->pipe_bpp = 24;
> +		break;
> +	case PIPECONF_10BPC:
> +		pipe_config->pipe_bpp = 30;
> +		break;
> +	case PIPECONF_12BPC:
> +		pipe_config->pipe_bpp = 36;
> +		break;
> +	default:
> +		break;
> +	}
> +
>  	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
>  		struct intel_shared_dpll *pll;
>  
> @@ -8630,6 +8663,9 @@ intel_pipe_config_compare(struct drm_device *dev,
>  	PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
>  
> +	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
> +		PIPE_CONF_CHECK_I(pipe_bpp);
> +
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_FLAGS
> -- 
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2013-09-13 11:56 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-06 20:28 [PATCH 00/11] drm/i915: adjusted_mode.clock vs. port_clock v3 ville.syrjala
2013-09-06 20:28 ` [PATCH 01/11] drm/i915: Don't factor in pixel multplier when deriving dotclock from link clock and M/N values ville.syrjala
2013-09-06 20:28 ` [PATCH v2 02/11] drm/i915: Make adjusted_mode.clock non-pixel multiplied ville.syrjala
2013-09-13 11:40   ` Jani Nikula
2013-09-06 20:29 ` [PATCH v2 03/11] drm/i915: Add support for pipe_bpp readout ville.syrjala
2013-09-13 11:59   ` Jani Nikula [this message]
2013-09-06 20:29 ` [PATCH 04/11] drm/i915: Add state readout and checking for has_dp_encoder and dp_m_n ville.syrjala
2013-09-10 14:02   ` [PATCH v2] " ville.syrjala
2013-09-13 12:11     ` Jani Nikula
2013-09-06 20:29 ` [PATCH 05/11] drm/i915: Make intel_fuzzy_clock_check() take in arbitrary clocks ville.syrjala
2013-09-13 12:55   ` Daniel Vetter
2013-09-06 20:29 ` [PATCH 06/11] drm/i915: Add intel_dotclock_calculate() ville.syrjala
2013-09-13 12:30   ` Jani Nikula
2013-09-13 12:43     ` Ville Syrjälä
2013-09-13 12:59       ` [PATCH v2] " ville.syrjala
2013-09-16 11:14         ` Jani Nikula
2013-09-16 20:41           ` Daniel Vetter
2013-09-17  8:16             ` Ville Syrjälä
2013-09-06 20:29 ` [PATCH 07/11] drm/i915: Make i9xx_crtc_clock_get() use dpll_hw_state ville.syrjala
2013-09-13 12:40   ` Jani Nikula
2013-09-13 13:12     ` Ville Syrjälä
2013-09-13 13:18     ` [PATCH v2] " ville.syrjala
2013-09-13 13:44       ` Jani Nikula
2013-09-06 20:29 ` [PATCH 08/11] drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs ville.syrjala
2013-09-08 12:35   ` Daniel Vetter
2013-09-09 11:06     ` [PATCH v2] " ville.syrjala
2013-09-13 13:04       ` Jani Nikula
2013-09-13 13:06         ` Ville Syrjälä
2013-09-13 13:47           ` Jani Nikula
2013-09-13 13:54             ` Ville Syrjälä
2013-09-16 20:43             ` Daniel Vetter
2013-09-06 20:29 ` [PATCH 09/11] drm/i915: Fix port_clock and adjusted_mode.clock readout all over ville.syrjala
2013-09-08 12:37   ` Daniel Vetter
2013-09-09 10:35     ` [PATCH v2] " ville.syrjala
2013-09-09 11:34       ` [PATCH v3] " ville.syrjala
2013-09-13 13:00         ` [PATCH v4] " ville.syrjala
2013-09-16 11:16           ` Jani Nikula
2013-09-06 20:29 ` [PATCH v2 10/11] drm/i915: Add PIPE_CONF_CHECK_CLOCK_FUZZY() ville.syrjala
2013-09-06 20:29 ` [PATCH v2 11/11] drm/i915: Add fuzzy clock check for port_clock ville.syrjala
2013-09-16 21:16   ` Daniel Vetter
2013-09-08 12:38 ` [PATCH 00/11] drm/i915: adjusted_mode.clock vs. port_clock v3 Daniel Vetter

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