From: Thomas Gleixner <tglx@kernel.org>
To: Michael Kelley <mhklinux@outlook.com>,
LKML <linux-kernel@vger.kernel.org>
Cc: "x86@kernel.org" <x86@kernel.org>,
Dmitry Ilvokhin <d@ilvokhin.com>, Radu Rendec <radu@rendec.net>,
Jan Kiszka <jan.kiszka@siemens.com>,
Kieran Bingham <kbingham@kernel.org>,
Florian Fainelli <florian.fainelli@broadcom.com>,
Marc Zyngier <maz@kernel.org>
Subject: RE: [patch V5 00/15] Improve /proc/interrupts further
Date: Thu, 02 Apr 2026 15:46:01 +0200 [thread overview]
Message-ID: <87qzox79wm.ffs@tglx> (raw)
In-Reply-To: <SN6PR02MB415762C7718ECDBD0D127A60D451A@SN6PR02MB4157.namprd02.prod.outlook.com>
On Thu, Apr 02 2026 at 02:32, Michael Kelley wrote:
> From: Thomas Gleixner <tglx@kernel.org> Sent: Wednesday, April 1, 2026 2:51 PM
> The improved alignment looks good. But if you want to be picky
> about the alignment, I noticed these things:
>
> On x86, the leftmost column now correctly aligns the "VPMI:" label.
> But the rightmost column does not correctly align the text
> "Perf Guest Mediated PMI". It needs one additional space. Here's my
> output (with some CPU columns removed so it's not so wide):
>
> root@mhkubun:~# cat /proc/interrupts | cut -b 1-30,64-
> CPU0 CPU1 CPU5 CPU6 CPU7
> 8: 0 0 0 0 0 IO-APIC 8-edge rtc0
> 9: 0 0 0 0 0 IO-APIC 9-fasteoi acpi
> NMI: 0 0 0 0 0 Non-maskable interrupts
> LOC: 0 0 0 0 0 Local timer interrupts
> PMI: 0 0 0 0 0 Performance monitoring interrupts
> IWI: 1 0 0 0 0 IRQ work interrupts
> RES: 325 231 235 341 231 Rescheduling interrupts
> CAL: 11547 7178 9033 8798 6738 Function call interrupts
> TLB: 0 0 0 0 0 TLB shootdowns
> TRM: 0 0 0 0 0 Thermal event interrupt
> THR: 0 0 0 0 0 Threshold APIC interrupts
> MCE: 0 0 0 0 0 Machine check exceptions
> MCP: 3 3 3 3 3 Machine check polls
> HYP: 7300 5185 278 6960 1213 Hypervisor callback interrupts
> HRE: 0 0 0 0 0 Hyper-V reenlightenment interrupts
> HVS: 8963 4359 9784 8374 61709 Hyper-V stimer0 interrupts
> PIN: 0 0 0 0 0 Posted-interrupt notification event
> NPI: 0 0 0 0 0 Nested posted-interrupt event
> PIW: 0 0 0 0 0 Posted-interrupt wakeup event
> VPMI: 0 0 0 0 0 Perf Guest Mediated PMI
That's weird. Let me have a look.
> On arm64, the leftmost column doesn't align the IPI<n> entries.
> Neither does the rightmost column for the IPI<n> entries. Here's some
> of my output:
>
> 45: 0 0 80 0 0 HV-PCI-MSIX-0817:00:02.0 14 Edge mlx5_comp13@pci:0817:00:02.0
> 46: 0 0 0 10 0 HV-PCI-MSIX-0817:00:02.0 15 Edge mlx5_comp14@pci:0817:00:02.0
> 47: 0 0 0 0 45 HV-PCI-MSIX-0817:00:02.0 16 Edge mlx5_comp15@pci:0817:00:02.0
> IPI0: 906 536 649 495 606 Rescheduling interrupts
> IPI1: 28844 12457 14770 55242 39175 Function call interrupts
> IPI2: 0 0 0 0 0 CPU stop interrupts
> IPI3: 0 0 0 0 0 CPU stop NMIs
> IPI4: 0 0 0 0 0 Timer broadcast interrupts
> IPI5: 11 1 5 0 2 IRQ work interrupts
> IPI6: 0 0 0 0 0 CPU backtrace interrupts
> IPI7: 0 0 0 0 0 KGDB roundup interrupts
> Err: 0
So the problem is that the default width for the interupt number is 3,
while the IPI entries need 4. I can I make that default to 4.
The text of the IPIs is prepadded in arm64's arch_show_interrupts().
next prev parent reply other threads:[~2026-04-02 13:46 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-01 21:51 [patch V5 00/15] Improve /proc/interrupts further Thomas Gleixner
2026-04-01 21:51 ` [patch V5 01/15] x86/irq: Optimize interrupts decimals printing Thomas Gleixner
2026-04-01 21:51 ` [patch V5 02/15] genirq/proc: Avoid formatting zero counts in /proc/interrupts Thomas Gleixner
2026-04-01 21:51 ` [patch V5 03/15] genirq/proc: Utilize irq_desc::tot_count to avoid evaluation Thomas Gleixner
2026-04-01 21:51 ` [patch V5 04/15] x86/irq: Make irqstats array based Thomas Gleixner
2026-04-01 21:51 ` [patch V5 05/15] x86/irq: Suppress unlikely interrupt stats by default Thomas Gleixner
2026-04-02 16:39 ` Radu Rendec
2026-05-11 14:38 ` Thomas Gleixner
2026-04-01 21:52 ` [patch V5 06/15] x86/irq: Move IOAPIC misrouted and PIC/APIC error counts into irq_stats Thomas Gleixner
2026-04-02 16:41 ` Radu Rendec
2026-04-01 21:52 ` [patch V5 07/15] scripts/gdb: Update x86 interrupts to the array based storage Thomas Gleixner
2026-04-02 17:11 ` Radu Rendec
2026-04-01 21:52 ` [patch V5 08/15] genirq: Expose nr_irqs in core code Thomas Gleixner
2026-04-01 21:52 ` [patch V5 09/15] genirq/manage: Make NMI cleanup RT safe Thomas Gleixner
2026-04-01 21:52 ` [patch V5 10/15] genirq: Cache the condition for /proc/interrupts exposure Thomas Gleixner
2026-04-02 17:27 ` Radu Rendec
2026-04-01 21:52 ` [patch V5 11/15] genirq: Calculate precision only when required Thomas Gleixner
2026-04-01 21:52 ` [patch V5 12/15] genirq: Add rcuref count to struct irq_desc Thomas Gleixner
2026-04-01 21:52 ` [patch V5 13/15] genirq: Expose irq_find_desc_at_or_after() in core code Thomas Gleixner
2026-04-01 21:52 ` [patch V5 14/15] genirq/proc: Runtime size the chip name Thomas Gleixner
2026-04-01 21:52 ` [patch V5 15/15] genirq/proc: Speed up /proc/interrupts iteration Thomas Gleixner
2026-04-02 2:32 ` [patch V5 00/15] Improve /proc/interrupts further Michael Kelley
2026-04-02 13:46 ` Thomas Gleixner [this message]
2026-05-11 15:45 ` Thomas Gleixner
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