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Mon, 19 May 2025 09:05:55 -0700 (PDT) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a35ca88735sm13600780f8f.69.2025.05.19.09.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 May 2025 09:05:54 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id D077D5F7EE; Mon, 19 May 2025 17:05:53 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Manos Pitsidianakis Cc: qemu-devel@nongnu.org, Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH] gdbstub: update aarch64-core.xml In-Reply-To: (Manos Pitsidianakis's message of "Mon, 19 May 2025 16:45:21 +0300") References: <20250519-gdbstub-aarch64-pstate-xml-v1-1-b4dbe87fe7c6@linaro.org> <87msb8sqts.fsf@draig.linaro.org> User-Agent: mu4e 1.12.11; emacs 30.1 Date: Mon, 19 May 2025 17:05:53 +0100 Message-ID: <87r00kr3fi.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Manos Pitsidianakis writes: > On Mon, 19 May 2025 15:55, Alex Benn=C3=A9e wrot= e: >>Manos Pitsidianakis writes: >> >>> Update aarch64-core.xml to include field definitions for PSTATE, which >>> in gdb is modelled in the cpsr (current program status register) >>> pseudo-register, named after the actual cpsr register in armv7. >>> >>> Defining the fields layout of the register allows easy inspection of for >>> example, the current exception level (EL): >>> >>> For example. Before booting a Linux guest, EL=3D2, but after booting and >>> Ctrl-C'ing in gdb, we get EL=3D0: >>> >>> (gdb) info registers $cpsr >>> cpsr 0x20402009 [ SP EL=3D2 BTYPE=3D0 PAN C ] >>> (gdb) cont >>> Continuing. >>> ^C >>> Thread 2 received signal SIGINT, Interrupt. >>> 0x0000ffffaaff286c in ?? () >>> (gdb) info registers $cpsr >>> cpsr 0x20001000 [ EL=3D0 BTYPE=3D0 SSBS C ] >>> >>> The aarch64-core.xml has been updated to match exactly the version >>> retrieved from upstream gdb, retrieved in 2025-05-19 from HEAD commit >>> 9f4dc0b137c86f6ff2098cb1ab69442c69d6023d. >>> >>> https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dtree;h=3D9f4dc0b13= 7c86f6ff2098cb1ab69442c69d6023d >>> >>> Signed-off-by: Manos Pitsidianakis >> >>Queued to gdbstub/next, thanks. >> > > Would patches for the field system registers (NZCV, CurrentEL, DAIF,=20 > SPSel) be acceptable? > > If yes, I think defining them in the static core xml is cleaner than=20 > generating them dynamically in "system-registers.xml" like we do with=20 > arm_gen_dynamic_sysreg_feature() but both can work. The drawback would=20 > be that we wouldn't match upstream gdb's core xml schema anymore. (Maybe= =20 > we can add a new xml include "pstate.xml" instead) You could submit to the gdb core schema first (surely they would also benefit from the patch?). --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro