Re: [PATCH v4 3/4] target/sh4: Rename TCGv variables as manual for ADDV opcode

[Yoshinori Sato <ysato@users.sourceforge.jp>]

On Wed, 01 May 2024 01:31:24 +0900,
Philippe Mathieu-Daudé wrote:
> 
> To easily compare with the SH4 manual, rename:
> 
>   REG(B11_8) -> Rn
>   REG(B7_4) -> Rm
>   t0 -> result
> 
> Mention how overflow is calculated.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/sh4/translate.c | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 3e013b7c7c..47c0f3404e 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -705,16 +705,20 @@ static void _decode_opc(DisasContext * ctx)
>          return;
>      case 0x300f: /* addv Rm,Rn */
>          {
> -            TCGv t0, t1, t2;
> -            t0 = tcg_temp_new();
> -            tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8));
> +            TCGv Rn = REG(B11_8);
> +            TCGv Rm = REG(B7_4);
> +            TCGv result, t1, t2;
> +
> +            result = tcg_temp_new();
>              t1 = tcg_temp_new();
> -            tcg_gen_xor_i32(t1, t0, REG(B11_8));
>              t2 = tcg_temp_new();
> -            tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
> +            tcg_gen_add_i32(result, Rm, Rn);
> +            /* T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 */
> +            tcg_gen_xor_i32(t1, result, Rn);
> +            tcg_gen_xor_i32(t2, Rm, Rn);
>              tcg_gen_andc_i32(cpu_sr_t, t1, t2);
>              tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
> -            tcg_gen_mov_i32(REG(B11_8), t0);
> +            tcg_gen_mov_i32(Rn, result);
>          }
>          return;
>      case 0x2009: /* and Rm,Rn */
> -- 
> 2.41.0
> 

Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>

-- 
Yosinori Sato