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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB3710.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 961c878e-e2ec-4dfe-9bff-08dbcc36ceac X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Oct 2023 21:53:17.0538 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: p/dI5LwLcMpAg+xCDoCekKTyYvBai3VopCe9wFo+tYxsqmQH+wFPXtDN39GZedo7tzu1YAyCybgtBHNBms2icKmi6c27U8lSCwS92iUa6VU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB8903 X-Proofpoint-ORIG-GUID: Sh8Ht7mX0bHKbH9DvRuhR3OCshz_pxwq X-Proofpoint-GUID: Sh8Ht7mX0bHKbH9DvRuhR3OCshz_pxwq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-13_12,2023-10-12_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 clxscore=1015 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310130190 Volodymyr Babchuk writes: > From: Oleksandr Andrushchenko > > Xen and/or Dom0 may have put values in PCI_COMMAND which they expect > to remain unaltered. PCI_COMMAND_SERR bit is a good example: while the > guest's view of this will want to be zero initially, the host having set > it to 1 may not easily be overwritten with 0, or else we'd effectively > imply giving the guest control of the bit. Thus, PCI_COMMAND register nee= ds > proper emulation in order to honor host's settings. > > According to "PCI LOCAL BUS SPECIFICATION, REV. 3.0", section "6.2.2 > Device Control" the reset state of the command register is typically 0, > so when assigning a PCI device use 0 as the initial state for the guest's= view > of the command register. > > Here is the full list of command register bits with notes about > emulation, along with QEMU behavior in the same situation: > > PCI_COMMAND_IO - QEMU does not allow a guest to change value of this bit > in real device. Instead it is always set to 1. A guest can write to this > register, but writes are ignored. > > PCI_COMMAND_MEMORY - QEMU behaves exactly as with PCI_COMMAND_IO. In > Xen case, we handle writes to this bit by mapping/unmapping BAR > regions. For devices assigned to DomUs, memory decoding will be > disabled and the initialization. > > PCI_COMMAND_MASTER - Allow guest to control it. QEMU passes through > writes to this bit. > > PCI_COMMAND_SPECIAL - Guest can generate special cycles only if it has > access to host bridge that supports software generation of special > cycles. In our case guest has no access to host bridges at all. Value > after reset is 0. QEMU passes through writes of this bit, we will do > the same. > > PCI_COMMAND_INVALIDATE - Allows "Memory Write and Invalidate" commands > to be generated. It requires additional configuration via Cacheline > Size register. We are not emulating this register right now and we > can't expect guest to properly configure it. QEMU "emulates" access to > Cachline Size register by ignoring all writes to it. QEMU passes through > writes of PCI_COMMAND_INVALIDATE bit, we will do the same. > > PCI_COMMAND_VGA_PALETTE - Enable VGA palette snooping. QEMU passes > through writes of this bit, we will do the same. > > PCI_COMMAND_PARITY - Controls how device response to parity > errors. QEMU ignores writes to this bit, we will do the same. > > PCI_COMMAND_WAIT - Reserved. Should be 0, but QEMU passes > through writes of this bit, so we will do the same. > > PCI_COMMAND_SERR - Controls if device can assert SERR. QEMU ignores > writes to this bit, we will do the same. > > PCI_COMMAND_FAST_BACK - Optional bit that allows fast back-to-back > transactions. It is configured by firmware, so we don't want guest to > control it. QEMU ignores writes to this bit, we will do the same. > > PCI_COMMAND_INTX_DISABLE - Disables INTx signals. If MSI(X) is > enabled, device is prohibited from asserting INTx as per > specification. Value after reset is 0. In QEMU case, it checks of INTx > was mapped for a device. If it is not, then guest can't control > PCI_COMMAND_INTX_DISABLE bit. In our case, we prohibit a guest to > change value of this bit if MSI(X) is enabled. > > Signed-off-by: Oleksandr Andrushchenko > Signed-off-by: Volodymyr Babchuk > --- > In v10: > - Added cf_check attribute to guest_cmd_read > - Removed warning about non-zero cmd > - Updated comment MSI code regarding disabling INTX > - Used ternary operator in vpci_add_register() call > - Disable memory decoding for DomUs in init_bars() > In v9: > - Reworked guest_cmd_read > - Added handling for more bits > Since v6: > - fold guest's logic into cmd_write > - implement cmd_read, so we can report emulated INTx state to guests > - introduce header->guest_cmd to hold the emulated state of the > PCI_COMMAND register for guests > Since v5: > - add additional check for MSI-X enabled while altering INTX bit > - make sure INTx disabled while guests enable MSI/MSI-X > Since v3: > - gate more code on CONFIG_HAS_MSI > - removed logic for the case when MSI/MSI-X not enabled > --- > xen/drivers/vpci/header.c | 44 +++++++++++++++++++++++++++++++++++---- > xen/drivers/vpci/msi.c | 6 ++++++ > xen/drivers/vpci/msix.c | 4 ++++ > xen/include/xen/vpci.h | 3 +++ > 4 files changed, 53 insertions(+), 4 deletions(-) > > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c > index efce0bc2ae..e8eed6a674 100644 > --- a/xen/drivers/vpci/header.c > +++ b/xen/drivers/vpci/header.c > @@ -501,14 +501,32 @@ static int modify_bars(const struct pci_dev *pdev, = uint16_t cmd, bool rom_only) > return 0; > } > =20 > +/* TODO: Add proper emulation for all bits of the command register. */ > static void cf_check cmd_write( > const struct pci_dev *pdev, unsigned int reg, uint32_t cmd, void *da= ta) > { > struct vpci_header *header =3D data; > =20 > + if ( !is_hardware_domain(pdev->domain) ) > + { > + const struct vpci *vpci =3D pdev->vpci; > + uint16_t excluded =3D PCI_COMMAND_PARITY | PCI_COMMAND_SERR | > + PCI_COMMAND_FAST_BACK; > + > + header->guest_cmd =3D cmd; > + > + if ( (vpci->msi && vpci->msi->enabled) || > + (vpci->msix && vpci->msi->enabled) ) There is a nasty mistake. It should be (vpci->msix && vpci->msix->enabled) > + excluded |=3D PCI_COMMAND_INTX_DISABLE; > + > + cmd &=3D ~excluded; > + cmd |=3D pci_conf_read16(pdev->sbdf, reg) & excluded; > + } > + > /* > - * Let Dom0 play with all the bits directly except for the memory > - * decoding one. > + * Let guest play with all the bits directly except for the memory > + * decoding one. Bits that are not allowed for DomU are already > + * handled above. > */ > if ( header->bars_mapped !=3D !!(cmd & PCI_COMMAND_MEMORY) ) > /* > @@ -522,6 +540,14 @@ static void cf_check cmd_write( > pci_conf_write16(pdev->sbdf, reg, cmd); > } > =20 > +static uint32_t cf_check guest_cmd_read( > + const struct pci_dev *pdev, unsigned int reg, void *data) > +{ > + const struct vpci_header *header =3D data; > + > + return header->guest_cmd; > +} > + > static void cf_check bar_write( > const struct pci_dev *pdev, unsigned int reg, uint32_t val, void *da= ta) > { > @@ -737,8 +763,9 @@ static int cf_check init_bars(struct pci_dev *pdev) > } > =20 > /* Setup a handler for the command register. */ > - rc =3D vpci_add_register(pdev->vpci, vpci_hw_read16, cmd_write, PCI_= COMMAND, > - 2, header); > + rc =3D vpci_add_register(pdev->vpci, > + is_hwdom ? vpci_hw_read16 : guest_cmd_read, > + cmd_write, PCI_COMMAND, 2, header); > if ( rc ) > return rc; > =20 > @@ -750,6 +777,15 @@ static int cf_check init_bars(struct pci_dev *pdev) > if ( cmd & PCI_COMMAND_MEMORY ) > pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd & ~PCI_COMMAND_MEM= ORY); > =20 > + /* > + * Clear PCI_COMMAND_MEMORY for DomUs, so they will always start wit= h > + * memory decoding disabled and to ensure that we will not call modi= fy_bars() > + * at the end of this function. > + */ > + if ( !is_hwdom ) > + cmd &=3D ~PCI_COMMAND_MEMORY; > + header->guest_cmd =3D cmd; > + > for ( i =3D 0; i < num_bars; i++ ) > { > uint8_t reg =3D PCI_BASE_ADDRESS_0 + i * 4; > diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c > index 2faa54b7ce..0920bd071f 100644 > --- a/xen/drivers/vpci/msi.c > +++ b/xen/drivers/vpci/msi.c > @@ -70,6 +70,12 @@ static void cf_check control_write( > =20 > if ( vpci_msi_arch_enable(msi, pdev, vectors) ) > return; > + > + /* > + * Make sure guest doesn't enable INTx while enabling MSI. > + */ > + if ( !is_hardware_domain(pdev->domain) ) > + pci_intx(pdev, false); > } > else > vpci_msi_arch_disable(msi, pdev); > diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c > index b6abab47ef..9d0233d0e3 100644 > --- a/xen/drivers/vpci/msix.c > +++ b/xen/drivers/vpci/msix.c > @@ -97,6 +97,10 @@ static void cf_check control_write( > for ( i =3D 0; i < msix->max_entries; i++ ) > if ( !msix->entries[i].masked && msix->entries[i].updated ) > update_entry(&msix->entries[i], pdev, i); > + > + /* Make sure guest doesn't enable INTx while enabling MSI-X. */ > + if ( !is_hardware_domain(pdev->domain) ) > + pci_intx(pdev, false); > } > else if ( !new_enabled && msix->enabled ) > { > diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h > index c5301e284f..60bdc10c13 100644 > --- a/xen/include/xen/vpci.h > +++ b/xen/include/xen/vpci.h > @@ -87,6 +87,9 @@ struct vpci { > } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; > /* At most 6 BARS + 1 expansion ROM BAR. */ > =20 > + /* Guest view of the PCI_COMMAND register. */ > + uint16_t guest_cmd; > + > /* > * Store whether the ROM enable bit is set (doesn't imply ROM BA= R > * is mapped into guest p2m) if there's a ROM BAR on the device. --=20 WBR, Volodymyr=